SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

• US 20180286950A1
• Filed: 03/06/2018
• Published: 10/04/2018
• Est. Priority Date: 03/29/2017
• Status: Active Grant

• Current Assignee: Asahi Kasei Microdevices Corporation (Asahi Kasei Corporation)
• Original Assignee: Asahi Kasei Microdevices Corporation (Asahi Kasei Corporation)
• Inventors: Fujii, Shuntaro
• Granted Patent: US 10,446,645 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/2253 by ion implantation
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 21/28052 the conductor comprising a silicide layer formed by the silicidation reaction of silicon with a metal layer formed by metal ion implantation H01L21/28044
• CPC Class Codes: H01L 21/28518 the conductive layers comprising silicides H01L21/28537 takes precedence
• CPC Class Codes: H01L 21/324 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/20 - H01L21/288 and H01L21/302 - H01L21/322 take precedence
• CPC Class Codes: H01L 21/74 Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
• CPC Class Codes: H01L 29/1041 with a non-uniform doping structure in the channel region surface
• CPC Class Codes: H01L 29/1083 with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
• CPC Class Codes: H01L 29/167 further characterised by the doping material H01L29/1604 takes precedence
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/4933 with a silicide layer contacting the silicon layer, e.g. Polycide gate with a barrier layer between the silicide and silicon layers H01L29/4941
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/66537 using a self aligned punch through stopper or threshold implant under the gate region H01L29/66606 takes precedence
• CPC Class Codes: H01L 29/66575 where the source and drain or source and drain extensions are self-aligned to the sides of the gate H01L29/66606 takes precedence
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618

Abstract

To reduce a 1/f noise of an insulated gate field effect transistor.

A semiconductor device 1 includes: a well region 5 provided on a surface layer of a semiconductor substrate 2; a source region 14S and a drain region 15D disposed to be distant from each other on the surface layer of the well region 5; a channel region 6 provided between the source region 14S and the drain region 15D; and a gate electrode 8 provided over the channel region 6 with a gate insulator 7 interposed therebetween. A gate length of the gate electrode 8 is 1.5 μm or less, the channel region 6 includes indium as a channel impurity, a distance between a surface of the channel region 6 and a concentration peak position of the channel impurity is 20 nm to 70 nm, and a concentration of the channel impurity gradually decreases in a direction from the concentration peak position of the channel impurity to the surface of the channel region.

Claims

1. A semiconductor device comprising:

a well region provided on a surface layer of a semiconductor substrate;

a source region and a drain region disposed to be distant from each other on a surface layer of the well region;

a channel region provided between the source region and the drain region; and

a gate electrode provided over the channel region with a gate insulator interposed between the gate electrode and the channel region,

wherein a gate length of the gate electrode is 1.5 μ

m or less,

the channel region includes indium as a channel impurity,

a distance between a surface of the channel region and a concentration peak position of the channel impurity is 20 nm to 70 nm, and

a concentration of the channel impurity gradually decreases in a direction from the concentration peak position of the channel impurity to the surface of the channel region.

2. The semiconductor device according to claim 1,

wherein an interface state density of the channel region is 3.0×

10⁹ cm<sup>−

2</sup> or higher and lower than 1.0×

10¹⁰ cm<sup>−

2</sup>.

3. The semiconductor device according to claim 1, further comprising:

a side wall spacer provided on a side surface of the gate electrode; and

a silicide layer provided on a surface of each of the gate electrode, the source region, and the drain region.

9. The semiconductor device according to claim 2, further comprising:

a side wall spacer provided on a side surface of the gate electrode; and

a silicide layer provided on a surface of each of the gate electrode, the source region, and the drain region.

4. A method of manufacturing a semiconductor device comprising:

ion-implanting a well impurity into a surface layer of a semiconductor substrate;

implanting an indium ion as a channel impurity into the surface layer of the semiconductor substrate;

performing a first heat treatment on the semiconductor substrate into which the well impurity and the indium ion have been implanted;

forming a gate insulator on the surface layer of the semiconductor substrate on which the first heat treatment has been performed;

forming a polysilicon film on the gate insulator;

performing a second heat treatment on the semiconductor substrate on which the polysilicon film has been formed after the formation of the polysilicon film; and

forming a gate electrode having an gate length of 1.5 μ

m or less by ion-implanting a gate impurity into the polysilicon film, patterning the polysilicon film, and performing a third heat treatment on the semiconductor substrate.

5. The method of manufacturing a semiconductor device according to claim 4,

wherein the second heat treatment is performed at a temperature of 965°

C. to 1125°

C.

6. The method of manufacturing a semiconductor device according to claim 5,

wherein the second heat treatment is performed for 15 seconds to 60 seconds.

7. The method of manufacturing a semiconductor device according to claim 4, further comprising:

forming an extension region including an extension impurity by ion-implanting the extension impurity into the surface layer of the semiconductor substrate by using the gate electrode as a mask, and performing a fourth heat treatment;

forming a side wall spacer on a side surface of the gate electrode; and

forming a contact region including a contact impurity by implanting the contact impurity into the surface layer of the semiconductor substrate more deeply than the extension impurity by using the gate electrode and the side wall spacer as a mask, and performing a fifth heat treatment on the semiconductor substrate.

8. The method of manufacturing a semiconductor device according to claim 7, further comprising:

forming a silicide layer on a surface of each of the gate electrode and the contact region.

10. The method of manufacturing a semiconductor device according to claim 5, further comprising:

forming an extension region including an extension impurity by ion-implanting the extension impurity into the surface layer of the semiconductor substrate by using the gate electrode as a mask, and performing a fourth heat treatment;

forming a side wall spacer on a side surface of the gate electrode; and

forming a contact region including a contact impurity by implanting the contact impurity into the surface layer of the semiconductor substrate more deeply than the extension impurity by using the gate electrode and the side wall spacer as a mask, and performing a fifth heat treatment on the semiconductor substrate.

11. The method of manufacturing a semiconductor device according to claim 6, further comprising:

forming an extension region including an extension impurity by ion-implanting the extension impurity into the surface layer of the semiconductor substrate by using the gate electrode as a mask, and performing a fourth heat treatment;

forming a side wall spacer on a side surface of the gate electrode; and

forming a contact region including a contact impurity by implanting the contact impurity into the surface layer of the semiconductor substrate more deeply than the extension impurity by using the gate electrode and the side wall spacer as a mask, and performing a fifth heat treatment on the semiconductor substrate.