LOW POWER EDGE AND DATA SAMPLING
1 Assignment
0 Petitions
Accused Products
Abstract
An integrated circuit receiver is disclosed comprising a data receiving circuit responsive to a timing signal to detect a data signal and an edge receiving circuit responsive to the timing signal to detect a transition of the data signal. One of the data or edge receiving circuits comprises an integrating receiver circuit while the other of the data or edge sampling circuits comprises a sampling receiver circuit.
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Citations
21 Claims
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1. (canceled)
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2. An integrated circuit receiver comprising:
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a data receiving circuit responsive to a timing signal to detect a data signal level within a valid data region of the data signal; an edge receiving circuit responsive to the timing signal to detect a signal level in a transition region of the data signal, the transition region at an end of the valid data range; and wherein the edge receiving circuit comprises an integrating receiver circuit. - View Dependent Claims (3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A method of operation in an integrated circuit receiver, the method comprising:
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receiving a data signal having a valid data region and a transition region; receiving a timing signal created synchronous with the data signal; detecting a data value in the valid data region in response to the timing signal; detecting an edge value in the transition region in response to the timing signal to generate early/late information; wherein detecting an edge value in the transition region comprises integrating in response to the timing signal. - View Dependent Claims (13, 14, 15, 16)
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17. A signaling system comprising:
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a first integrated circuit device including a transmitter circuit to transmit a data signal and an accompanying timing signal, the timing signal created synchronous with the data signal; a second integrated circuit device including a receiver circuit to receive the data signal and timing signal, the receiver circuit comprising a sampling receiver circuit responsive to a timing signal to detect a valid data region of a data signal; and an integrating receiver circuit responsive to the timing signal to detect a transition region associated with the data signal. - View Dependent Claims (18, 19, 20, 21)
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Specification