Radio-Frequency Apparatus with Improved Power Consumption and Associated Methods

• US 20180287832A1
• Filed: 03/29/2017
• Published: 10/04/2018
• Est. Priority Date: 03/29/2017
• Status: Abandoned Application

• Current Assignee: Silicon Laboratories Incorporated
• Original Assignee: Silicon Laboratories Incorporated
• Inventors: Zhou, Yan, Naik, Amey, Gou, He
• Application Number:
  US15/472,609
• Publication Number:
  US 20180287832A1
• Time in Patent Office: Days
• CPC Class Codes: H04W 4/70 Services for machine-to-machine communication [M2M] or machine type communication [MTC]
• CPC Class Codes: H04W 52/0203 in the radio access network or backbone network of wireless communication networks
• CPC Class Codes: H04W 52/245 taking into account received signal strength
• CPC Class Codes: H04W 52/52 using AGC [Automatic Gain Control] circuits or amplifiers
• CPC Class Codes: Y02D 30/70 in wireless communication networks

Abstract

An apparatus includes an RF receiver. The RF receiver includes digital signal arrival (DSA) circuitry to detect an arrival of a received signal in the RF receiver and to indicate arrival of the received signal. The RF receiver further includes detection circuitry to detect a signal from the received signal, and a controller to control operation of the detection circuitry depending on whether the DSA circuitry indicates the arrival of the received signal.

Claims

1. An apparatus, comprising:

a radio-frequency (RF) receiver, comprising

digital signal arrival (DSA) circuitry to detect an arrival of a received signal in the RF receiver and to indicate arrival of the received signal;

detection circuitry to detect a signal from the received signal; and

a controller to control operation of the detection circuitry depending on whether the DSA circuitry indicates the arrival of the received signal.

2. The apparatus according to claim 1, wherein the DSA circuitry operates on a subset of a set of bits comprising the received signal.

3. The apparatus according to claim 2, wherein the RF receiver further comprises a digital automatic gain control (AGC) circuit to select and provide the subset of bits to the DSA circuitry.

4. The apparatus according to claim 3, the RF receiver further comprises a channel filter coupled to the digital AGC circuit, and wherein the digital AGC circuit selects the subset of bits based on detecting a power of the received signal in the channel filter.

5. The apparatus according to claim 3, wherein the DSA circuitry comprises:

a complex multiplier coupled to the digital AGC circuit; and

a divider circuit coupled to the complex multiplier.

6. The apparatus according to claim 2, wherein the DSA circuitry comprises a correlator to operate on the subset of bits and to provide a correlator output signal.

7. The apparatus according to claim 6, wherein the DSA circuitry further comprises a comparator to compare a dynamic threshold value with a signal derived from the correlator output signal to determine arrival of the received signal.

8. The apparatus according to claim 7, wherein the DSA circuitry further comprises a peak check circuit coupled to receive an output of the comparator and to prevent false indication of the arrival of the received signal because of spurious signals.

9. The apparatus according to claim 1, wherein the controller controls the operation of the detection circuitry by selectively:

(a) interrupting power to the detection circuitry;

(b) inhibiting a clock signal of the detection circuitry;

or (c) disabling the detection circuitry.

10. An integrated circuit (IC), comprising:

a radio-frequency (RF) receiver, comprising;

digital signal arrival (DSA) circuitry comprising a correlator to operate on a subset of bits of a set of bits comprising a received signal in the RF receiver to reduce a power consumption of the correlator, the DSA circuitry to provide a signal indicating arrival of the received signal;

a controller to control operation of a detection circuitry depending on whether the DSA circuitry indicates the arrival of the received signal.

11. The IC according to claim 10, further comprising a digital automatic gain control (AGC) circuit to provide the subset of bits to the DSA circuitry.

12. The IC according to claim 10, wherein the DSA circuitry provides a signal indicating arrival of the received signal depending on whether an output signal of the correlator exceeds a dynamic threshold value.

13. The IC according to claim 10, wherein the DSA circuitry comprises a peak check circuit to check peaks of the output signal of the correlator to prevent false indication of the arrival of the received signal

14. The apparatus according to claim 10, wherein the received signal in the RF receiver is modulated according to IEEE 802.15.4 standard.

15. A method of processing signals in a radio-frequency (RF) receiver, the method comprising:

detecting arrival of a signal received in the RF receiver by using digital signal arrival (DSA) circuitry, and to indicate arrival of the received signal; and

selectively detecting a signal from the received signal depending on indication by the DSA circuitry of the arrival of the received signal.

16. The method according to claim 15, wherein detecting arrival of the signal received in the RF receiver further comprises using a subset of a set of bits comprising the received signal.

17. The method according to claim 16, wherein detecting arrival of the signal received in the RF receiver further comprises using a correlator to operate on the subset of bits in order to reduce a power consumption of the correlator.

18. The method according to claim 17, wherein detecting arrival of the signal received in the RF receiver further comprises:

comparing an output signal of the correlator with a dynamic threshold value; and

checking peaks in the output signal of the correlator to prevent false indication of the arrival of the received signal.

19. The method according to claim 15, selectively detecting a signal from the received signal further comprises selectively operating a detection circuitry.

20. The method according to claim 19, wherein selectively operating the detection circuitry further comprises:

(a) interrupting power to the detection circuitry;

(b) inhibiting a clock signal of the detection circuitry;

or (c) disabling the detection circuitry.