COMPOSING CORES AND FPGAS AT MASSIVE SCALE WITH DIRECTIONAL, TWO DIMENSIONAL ROUTERS AND INTERCONNECTION NETWORKS

• US 20180287964A1
• Filed: 04/04/2018
• Published: 10/04/2018
• Est. Priority Date: 04/04/2017
• Status: Active Grant

• Current Assignee: Grady Research, Inc.
• Original Assignee: Grady Research, Inc.
• Inventors: Gray, Jan Stephen
• Granted Patent: US 10,587,534 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 13/4282 on a serial bus, e.g. I2C bus, SPI bus on daisy chain buses G06F13/4247
• CPC Class Codes: G06F 2213/0026 PCI express
• CPC Class Codes: H04L 12/18 for broadcast or conference , e.g. multicast
• CPC Class Codes: H04L 49/109 Integrated on microchip, e.g. switch-on-chip

Abstract

Embodiments of systems and methods for sending messages between cores across multiple field programmable gate arrays (FPGAs) and other devices are disclosed. A uniform destination address directs a message to a core in any FPGA. Message routing within one FPGA may use a bufferless directional 2D torus Network on Chip (NOC). Message routing between FPGAs may use remote router cores coupled to the NOCs. A message from one core to another in another FPGA is routed over a NOC to a local remote router then to external remote router(s) across inter-FPGA links or networks to the remote router of the second FPGA and across a second NOC to the destination core. Messages may also be multicast to multiple cores across FPGAs. A segmented directional torus NOC is also disclosed. The insertion of shortcut routers into directional torus rings achieves shorter ring segments, reducing message delivery latency and increasing NOC bandwidth.

Claims

1. An apparatus, comprising:

a first FPGA including a first remote router, a first client core, and a first network on a chip communicatively coupled to the remote router and to the client core; and

a second FPGA including a second remote router, a second client core, and a second network on a chip communicatively coupled to the second remote router and to the second client core, the second FPGA configured to send a message from the second client core to the first client core by causing the message to travel from the second client core, to the second network on a chip, to the second remote router, to the first remote router, to the first network on a chip, and to the first client core.

2. The apparatus of claim 1, wherein:

the first network on a chip and the second network on a chip respectively include a first router circuit and a second router circuit; and

wherein the first router circuit includes a switch circuit having first- and second-dimension input nodes, a client input node, and first- and second-dimension output nodes.

3. The apparatus of claim 2, wherein the switch circuit includes a switch element that includes a dual-output look-up table configured:

to implement one bit of a first-dimension output multiplexer by selecting from one bit of each of the first-dimension input node, the second-dimension input node, and the client input node; and

to implement one bit of a second-dimension output multiplexer by selecting from the one bit of the first dimension input, the one bit of the second dimension input, and the one bit of the client input.

4. The apparatus of claim 1, further comprising a point-to-point interconnect configured to couple, communicatively, the first remote router to the second remote router.

5. The apparatus of claim 1, further comprising a PCI Express link configured to couple, communicatively, the first remote router to the second remote router.

6. The apparatus of claim 1, further comprising a PCI Express switch configured to couple, communicatively, the first remote router to the second remote router.

7. The apparatus of claim 1, further comprising an internet-protocol network configured to couple, communicatively, the first remote router to the second remote router.

8. The apparatus of claim 1, wherein:

the first FPGA includes a third client core communicatively coupled to the first network on a chip; and

the second client core is configured

to generate a multicast message, and

to send the multicast message to the first client core and to the third client core via the second network on a chip, the second remote router, the first remote router, and the first network on a chip.

9. The apparatus of claim 1, further comprising:

a third FPGA including a third remote router, a third client core, and a third network on a chip communicatively coupled to the third remote router and to the third client core; and

wherein the second client core of the second FPGA is configured

to generate a multicast message, and

to send the multicast message to the first client core of the first FPGA and to the third client core of the third FPGA.

10. The apparatus of claim 1, wherein the second client core includes a soft processor core.

11. The apparatus of claim 1, wherein the first client core includes an accelerator core.

12. The apparatus of claim 1, wherein the second client core includes a cluster of two or more processor cores.

13. The apparatus of claim 1, wherein the second client core includes a cluster of a processor core, an accelerator core, and a memory coupled to the processor core and to the accelerator core.

14-15. -15. (canceled)

16. An FPGA, comprising:

a first network on a chip;

a first client core communicatively coupled to the first network on a chip; and

a first remote router communicatively coupled to the first network on a chip and configured

to receive a message from a source off of the FPGA, and

to send the message to the first client core via the first network on a chip.

17. The FPGA of claim 16, wherein the first remote router is configured to receive the message from second client core of another FPGA via a second remote router and a second network on a chip of the other FPGA.

18. A method, comprising:

sending, from a first client core of a first FPGA to a first network on a chip of the first FPGA, a message and a destination address indicating that the destination of the message is a second client core of a second FPGA; and

in response to the destination address

sending the message and the destination address from the first network on a chip to a first remote router of the first FPGA,

sending the message and the destination address from the first remote router to a second remote router of the second FPGA,

sending the message and the destination address from the second remote router to a second network on a chip of the second FPGA, and

sending the message from the second network on a chip to the second client core.

19. The method of claim 18, further comprising, in response to the destination address:

accepting the message and the destination address from the second remote router with a first network-on-a-chip router of the second FPGA; and

wherein sending the message from the second remote router to the second client core includes

sending the message and the destination address from the first network-on-a-chip router to a second network-on-a-chip router of the second FPGA via the second network on a chip; and

sending the message from the second network-on-a-chip router to the second client core.

20. The method of claim 18 wherein:

sending the message and the destination address from the second remote router to the second network on a chip includes sending the message and the destination address to a first network-on-a-chip router of the second FPGA via the second network on a chip; and

sending the message from the second network on a chip to the second client core includes

sending the message and the destination address from the first network-on-a-chip router to a second network-on-a-chip router over a first-dimension link of the second network on a chip,

sending the message and the destination address from the second network-on-a-chip router to a third network-on-a-chip router over a second-dimension link of the second network on a chip, and

sending the message from the third network-on-a-chip router to the second client core.

21. The method of claim 18 wherein:

sending the message and the destination address from the second remote router to the second network on a chip includes sending the message and the destination address to a first network-on-a-chip router of the second FPGA via the second network on a chip; and

sending the message from the second network on a chip to the second client core includes

serially sending the message and the destination address from the first network-on-a-chip router to one or more additional network-on-a-chip routers along a first-dimension ring to which the first network-on-a-chip router belongs until the message is at a second network-on-a-chip router corresponding to a first-dimension coordinate of the destination address,

serially sending the message and the destination address from the second network-on-a-chip router to one or more additional network-on-a-chip routers along a second-dimension ring to which the second network-on-a-chip router belongs until the message is at a third network-on-a-chip router corresponding to the first-dimension coordinate and to the second-dimension coordinate of the destination address, and

sending the message form the third network-on-a-chip-router to the second client core.

22. The method of claim 18, wherein the destination address is part of the message.

23. The method of claim 18, further comprising sending the destination address from the second network on a chip to the second client core.

24-25. -25. (canceled)

26. A method, comprising:

receiving, with a first remote router of a first FPGA from a source off of the first FPGA, a message and a destination address indicating a client core of the first FPGA;

sending, in response to the destination address, the message and the destination address from the first remote router to a network on a chip of the first FPGA; and

sending, in response to the destination address, the message from the network on a chip to the client core.

27. The method of claim 26, wherein receiving the message and the destination address includes receiving the message and the destination address from a second remote router of a second FPGA.

28. The method of claim 26, further comprising sending, in response to the destination address, the destination address from the network on a chip to the client core.

29-38. -38. (canceled)

39. A non-transient machine-readable medium storing configuration data, that, when loaded into a programmable circuit array, causes the programmable circuit array to instantiate a circuit configured:

to send, from a first client core of a first FPGA to a first network on a chip of the first FPGA, a message and a destination address indicating that the destination of the message is a second client core of a second FPGA; and

in response to the destination address

to send the message and the destination address from the first network on a chip to a first remote router of the first FPGA,

to send the message and the destination address from the first remote router to a second remote router of the second FPGA,

to send the message and the destination address from the second remote router to a second network on a chip of the second FPGA, and

to send the message from the second network on a chip to the second client core.

40. (canceled)

41. A non-transient machine-readable medium storing configuration data, that, when loaded into a programmable circuit array, causes the programmable circuit array to instantiate a circuit configured:

to receive, with a first remote router of a first FPGA from a source off of the first FPGA, a message and a destination address indicating a client core of the first FPGA;

to send, in response to the destination address, the message and the destination address from the first remote router to a network on a chip of the first FPGA; and

to send, in response to the destination address, the message from the network on a chip to the client core.

42-43. -43. (canceled)