MANAGING LOCK AND UNLOCK OPERATIONS USING TRAFFIC PRIORITIZATION
First Claim
1. A processor comprising:
- a plurality of processor cores;
interconnection circuitry configured to connect each processor core to a memory system of the processor; and
instruction management circuitry configured to manage lock and unlock operations for first thread executing on a first processor core of the plurality of processor cores, the managing including;
for each instruction included in the first thread and identified as being associated with a lock operation corresponding to a particular lock, in response to determining that the particular lock has already been acquired, continuing to perform the lock operation for a plurality of attempts during which the first processor core is not able to execute threads other than the first thread, andfor each instruction included in the first thread and identified as being associated with an unlock operation corresponding to a particular lock, releasing the particular lock from the first thread;
wherein the interconnection circuitry is configured to preserve prioritization of selected messages associated with instructions identified as being associated with an unlock operation over messages associated with instructions identified as being associated with a lock operation.
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Accused Products
Abstract
Managing lock and unlock operations for a first thread executing on a first processor core includes, for each instruction included in the first thread and identified as being associated with: (1) a lock operation corresponding to a particular lock, in response to determining that the particular lock has already been acquired, continuing to perform the lock operation for multiple attempts during which the first processor core is not able to execute threads other than the first thread, or (2) an unlock operation corresponding to a particular lock, releasing the particular lock from the first thread. Prioritization of selected messages sent over interconnection circuitry configured to connect each processor core to a memory system of the processor is preserved. The selected messages associated with instructions identified as being associated with an unlock operation are prioritized over messages associated with instructions identified as being associated with a lock operation.
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Citations
20 Claims
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1. A processor comprising:
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a plurality of processor cores; interconnection circuitry configured to connect each processor core to a memory system of the processor; and instruction management circuitry configured to manage lock and unlock operations for first thread executing on a first processor core of the plurality of processor cores, the managing including; for each instruction included in the first thread and identified as being associated with a lock operation corresponding to a particular lock, in response to determining that the particular lock has already been acquired, continuing to perform the lock operation for a plurality of attempts during which the first processor core is not able to execute threads other than the first thread, and for each instruction included in the first thread and identified as being associated with an unlock operation corresponding to a particular lock, releasing the particular lock from the first thread; wherein the interconnection circuitry is configured to preserve prioritization of selected messages associated with instructions identified as being associated with an unlock operation over messages associated with instructions identified as being associated with a lock operation. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A method for managing instructions on a processor comprising a plurality of processor cores, the method comprising:
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managing lock and unlock operations for a first thread executing on a first processor core of the plurality of processor cores, the managing including; for each instruction included in the first thread and identified as being associated with a lock operation corresponding to a particular lock, in response to determining that the particular lock has already been acquired, continuing to perform the lock operation for a plurality of attempts during which the first processor core is not able to execute threads other than the first thread, and for each instruction included in the first thread and identified as being associated with an unlock operation corresponding to a particular lock, releasing the particular lock from the first thread; and preserving prioritization of selected messages sent over interconnection circuitry configured to connect each processor core to a memory system of the processor, where the selected messages associated with instructions identified as being associated with an unlock operation are prioritized over messages associated with instructions identified as being associated with a lock operation. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20)
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Specification