MANAGING LOCK AND UNLOCK OPERATIONS USING TRAFFIC PRIORITIZATION

• US 20180293100A1
• Filed: 05/31/2017
• Published: 10/11/2018
• Est. Priority Date: 04/05/2017
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: Cavium, LLC (Marvell Technology Group Limited)
• Inventors: Mukherjee, Shubhendu Sekhar, Akkawi, Isam Wadih, Asher, David, Bertone, Michael, Carlson, David Albert, Dobbie, Bradley, Kessler, Richard Eugene
• Granted Patent: US 10,445,096 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 9/3004 to perform operations on memory
• CPC Class Codes: G06F 9/30072 to perform conditional operations, e.g. using predicates or guards
• CPC Class Codes: G06F 9/30079 Pipeline control instructions, e.g. multicycle NOP
• CPC Class Codes: G06F 9/3009 Thread control instructions
• CPC Class Codes: G06F 9/3834 Maintaining memory consistency
• CPC Class Codes: G06F 9/4881 Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues
• CPC Class Codes: G06F 9/526 Mutual exclusion algorithms
• CPC Class Codes: G06F 9/528 by using speculative mechanisms
• CPC Class Codes: G06F 9/546 Message passing systems or structures, e.g. queues

Abstract

Managing lock and unlock operations for a first thread executing on a first processor core includes, for each instruction included in the first thread and identified as being associated with: (1) a lock operation corresponding to a particular lock, in response to determining that the particular lock has already been acquired, continuing to perform the lock operation for multiple attempts during which the first processor core is not able to execute threads other than the first thread, or (2) an unlock operation corresponding to a particular lock, releasing the particular lock from the first thread. Prioritization of selected messages sent over interconnection circuitry configured to connect each processor core to a memory system of the processor is preserved. The selected messages associated with instructions identified as being associated with an unlock operation are prioritized over messages associated with instructions identified as being associated with a lock operation.

Claims

1. A processor comprising:

a plurality of processor cores;

interconnection circuitry configured to connect each processor core to a memory system of the processor; and

instruction management circuitry configured to manage lock and unlock operations for first thread executing on a first processor core of the plurality of processor cores, the managing including;

for each instruction included in the first thread and identified as being associated with a lock operation corresponding to a particular lock, in response to determining that the particular lock has already been acquired, continuing to perform the lock operation for a plurality of attempts during which the first processor core is not able to execute threads other than the first thread, and

for each instruction included in the first thread and identified as being associated with an unlock operation corresponding to a particular lock, releasing the particular lock from the first thread;

wherein the interconnection circuitry is configured to preserve prioritization of selected messages associated with instructions identified as being associated with an unlock operation over messages associated with instructions identified as being associated with a lock operation.

2. The processor of claim 1, wherein the interconnection circuitry includes distinct electronic signal pathways associated with different communication channels of a plurality of communication channels.

3. The processor of claim 1, wherein continuing to perform the lock operation for a plurality of attempts includes using a hardware lock operation different from a lock operation in a stored library accessible to the first thread, after the lock operation in the stored library is invoked.

4. The processor of claim 3, wherein the hardware lock operation performs a modified atomic operation that changes a result of the hardware lock operation for failed attempts to acquire the particular lock relative to a result of the lock operation in the stored library.

5. The processor of claim 3, wherein the first processor core includes circuitry configured to identify selected instructions as being associated with operations from the stored library, the identifying including, for a plurality of instructions included in a particular thread executing on the processor, identifying a first subset of the plurality of instructions as being associated with a lock operation based on predetermined characteristics of the plurality of instructions, and identifying a second subset of the plurality of instructions as being associated with an unlock operation based on predetermined characteristics of the plurality of instructions.

6. The processor of claim 5, wherein the circuitry configured to identify selected instructions as being associated with operations from the stored library is included within issue logic circuitry of a pipeline stage of the first processor core.

7. The processor of claim 1, wherein, after a predetermined threshold on the plurality of attempts, the first processor core places the first thread into an inactive state that enables the first processor core to temporarily execute threads other than the first thread until the first thread is placed back into an active state.

8. The processor of claim 7, wherein, after releasing the particular lock from the first thread, the first processor core determines if there are any waiting threads executing on a processor core other than the first processor core that were placed into the inactive state after at least one attempt at acquiring the particular lock, and if so, places at least one waiting thread back into the active state.

9. The processor of claim 1, wherein continuing to perform the lock operation for a plurality of attempts includes using a lock operation in a stored library accessible to the first thread.

10. The processor of claim 1, wherein the first processor core is configured to prioritize:

(1) the selected messages associated with instructions identified as being associated with an unlock operation, and (2) any messages associated with store instructions that are destined for a cache block that is being targeted by a pointer of the unlock operation.

11. A method for managing instructions on a processor comprising a plurality of processor cores, the method comprising:

managing lock and unlock operations for a first thread executing on a first processor core of the plurality of processor cores, the managing including;

for each instruction included in the first thread and identified as being associated with a lock operation corresponding to a particular lock, in response to determining that the particular lock has already been acquired, continuing to perform the lock operation for a plurality of attempts during which the first processor core is not able to execute threads other than the first thread, and

for each instruction included in the first thread and identified as being associated with an unlock operation corresponding to a particular lock, releasing the particular lock from the first thread; and

preserving prioritization of selected messages sent over interconnection circuitry configured to connect each processor core to a memory system of the processor, where the selected messages associated with instructions identified as being associated with an unlock operation are prioritized over messages associated with instructions identified as being associated with a lock operation.

12. The method of claim 11, wherein the interconnection circuitry includes distinct electronic signal pathways associated with different communication channels of a plurality of communication channels.

13. The method of claim 11, wherein continuing to perform the lock operation for a plurality of attempts includes using a hardware lock operation different from a lock operation in a stored library accessible to the first thread, after the lock operation in the stored library is invoked.

14. The method of claim 13, wherein the hardware lock operation performs a modified atomic operation that changes a result of the hardware lock operation for failed attempts to acquire the particular lock relative to a result of the lock operation in the stored library.

15. The method of claim 13, wherein the first processor core identifies selected instructions as being associated with operations from the stored library, the identifying including, for a plurality of instructions included in a particular thread executing on the processor, identifying a first subset of the plurality of instructions as being associated with a lock operation based on predetermined characteristics of the plurality of instructions, and identifying a second subset of the plurality of instructions as being associated with an unlock operation based on predetermined characteristics of the plurality of instructions.

16. The method of claim 15, wherein the first processor core includes circuitry configured to identify selected instructions as being associated with operations from the stored library within issue logic circuitry of a pipeline stage of the first processor core.

17. The method of claim 11, wherein, after a predetermined threshold on the plurality of attempts, the first processor core places the first thread into an inactive state that enables the first processor core to temporarily execute threads other than the first thread until the first thread is placed back into an active state.

18. The method of claim 17, wherein, after releasing the particular lock from the first thread, the first processor core determines if there are any waiting threads executing on a processor core other than the first processor core that were placed into the inactive state after at least one attempt at acquiring the particular lock, and if so, places at least one waiting thread back into the active state.

19. The method of claim 11, wherein continuing to perform the lock operation for a plurality of attempts includes using a lock operation in a stored library accessible to the first thread.

20. The method of claim 11, wherein the first processor core prioritizes:

(1) the selected messages associated with instructions identified as being associated with an unlock operation, and (2) any messages associated with store instructions that are destined for a cache block that is being targeted by a pointer of the unlock operation.