LOW OVERHEAD EXCLUSIVE CONTROL FOR SHARED MEMORY OBJECTS

• US 20180293186A1
• Filed: 04/05/2017
• Published: 10/11/2018
• Est. Priority Date: 04/05/2017
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Katayama, Yasunao
• Granted Patent: US 10,585,818 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 13/1642 with request queuing
• CPC Class Codes: G06F 13/1663 Access to shared memory
• CPC Class Codes: G06F 13/1668 Details of memory controller
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G06F 13/42 Bus transfer protocol, e.g. handshake; Synchronisation
• CPC Class Codes: G06F 9/52 Program synchronisation; Mutual exclusion, e.g. by means of semaphores
• CPC Class Codes: G06F 9/526 Mutual exclusion algorithms
• CPC Class Codes: G06F 9/544 Buffers; Shared memory; Pipes

Abstract

A computer-implemented method is provided for exclusive control of shared memory objects. The method computer-implemented includes transmitting and performing a plurality of accesses to the shared memory objects from local and remote locations via read requests and write requests made to a memory, and controlling the read and write requests by a memory controller including a read queue, a write queue, and a lock address list. The computer-implemented method further includes initiating each read request to the memory via the memory controller whatever the corresponding lock bit is, initiating each write request to the memory from the recently read location via the memory controller when the corresponding lock bit is enabled, otherwise notify the requesting local or remote locations as incomplete, and enabling and disabling the corresponding lock bit after the initiation of the read and write requests to the memory, respectively.

Claims

1-14. -14. (canceled)

15. A computer system for exclusive control of shared memory objects, each node of the computer system comprising:

a memory; and

at least one processor in communication with the memory, wherein the computer system is configured to;

transmit and perform a plurality of accesses to the shared memory objects from local and remote locations via read requests and write requests made to a memory;

control the read and write requests by a memory controller including a read queue, a write queue, and a lock address list, each slot of the lock address list associated with a lock bit;

initiate each read request to the memory via the memory controller whatever the corresponding lock bit is;

initiate each write request to the memory from the recently read location via the memory controller when the corresponding lock bit is enabled, otherwise notify the requesting local or remote locations as incomplete; and

enable and disable the corresponding lock bit after the initiation of the read write requests to the memory, respectively.

16. The computer system of claim 15, wherein exclusive access controls with states and queues are handled near the memory.

17. The computer system of claim 15, wherein the memory controller arbitrates local and remote locations more equally.

18. The computer system of claim 15, wherein read-write constraints for multiple access is handled locally.

19. The computer system of claim 15, wherein the lock bits are segmented according to the memory controller'"'"'s access granularity.

20. The computer system of claim 15, wherein memory-based protocols executed by the memory controller are supported for IO memory access architectures such as Remote Direct Memory Access (RDMA).