COARSE GRAIN COHERENCY

• US 20180293693A1
• Filed: 04/09/2017
• Published: 10/11/2018
• Est. Priority Date: 04/09/2017
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Ray, Joydeep, Koker, Altug, Valerio, James A., Puffer, David, Appu, Abhishek R., Junkins, Stephen
• Granted Patent: US 10,373,285 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 12/0811 with multilevel cache hierarchies
• CPC Class Codes: G06F 12/0815 Cache consistency protocols
• CPC Class Codes: G06F 12/0831 using a bus scheme, e.g. with bus monitoring or watching means
• CPC Class Codes: G06F 12/0888 using selective caching, e.g. bypass
• CPC Class Codes: G06F 2212/1024 Latency reduction
• CPC Class Codes: G06F 2212/302 In image processor or graphics adapter
• CPC Class Codes: G06F 2212/621 Coherency control relating to peripheral accessing, e.g. from DMA or I/O device
• CPC Class Codes: G06F 2212/65 Details of virtual memory and virtual address translation
• CPC Class Codes: G06F 2212/656 Address space sharing
• CPC Class Codes: G06F 2212/657 Virtual address space management
• CPC Class Codes: G06T 1/20 Processor architectures; Processor configuration, e.g. pipelining
• CPC Class Codes: G06T 1/60 Memory management

Abstract

One embodiment provides for a general-purpose graphics processing device comprising a general-purpose graphics processing compute block to process a workload including graphics or compute operations, a first cache memory, and a coherency module enable the first cache memory to coherently cache data for the workload, the data stored in memory within a virtual address space, wherein the virtual address space shared with a separate general-purpose processor including a second cache memory that is coherent with the first cache memory.

Claims

1. A general-purpose graphics processing device comprising:

a general-purpose graphics processing compute block to process a workload including graphics or compute operations;

a first cache memory; and

a coherency module to enable the first cache memory to coherently cache data stored in memory within a virtual address space, wherein the virtual address space is shared with a separate general-purpose processor, the separate general-purpose processor including a second cache memory that is coherent with the first cache memory, wherein the coherency module tracks coherency for shared virtual memory at superline granularity, a superline including multiple cache lines.

2. The general-purpose graphics processing device as in claim 1, wherein the general-purpose graphics processing compute block includes multiple compute clusters, each compute cluster including multiple graphics multiprocessors.

3. The general-purpose graphics processing device as in claim 1, wherein the workload is a heterogeneous workload including operations to be performed by the general-purpose graphics processing compute block and the separate general-purpose processor.

4. The general-purpose graphics processing device as in claim 1, wherein the first cache memory is a level 3 cache memory.

5. The general-purpose graphics processing device as in claim 1, wherein the general-purpose graphics processing device is an add-in card connected to the separate general-purpose processor via a system bus.

6. The general-purpose graphics processing device as in claim 5, wherein the add-in card includes memory, the memory coupled with the general-purpose graphic processing device.

7. The general-purpose graphics processing device as in claim 6, wherein data storage for the first cache memory is managed at cache line granularity and coherence with the second cache memory is managed at superline granularity.

8. The general-purpose graphics processing device as in claim 7, additionally including a superline ownership table to store a set of superlines owned by the general-purpose graphics processing device.

9. The general-purpose graphics processing device as in claim 8, wherein the superline ownership table includes an entry for each superline in the set of superlines owned by the general-purpose graphics processing device.

10. The general-purpose graphics processing device as in claim 9, wherein each entry in the superline ownership table includes a superline tag and a coherency protocol status for the superline.

11. The general-purpose graphics processing device as in claim 10, wherein the coherency protocol status is one of modified, exclusive, shared, or invalid.

12. The general-purpose graphics processing device as in claim 10, each entry in the superline ownership table additionally includes a valid bit for each cache line within the superline.

13. A method on an agent of a heterogeneous processing system, the method comprising:

receiving a request to access a virtual memory address from a process executing on the agent;

determining if the agent has ownership of a first superline associated with the virtual memory address, the first superline associated with a memory region spanning multiple cache lines, wherein determining if the agent has ownership of the first superline includes reading an entry for the first superline from an on-die superline directory table cache;

accessing the virtual memory address from the agent without triggering a snoop request when the agent has ownership of the first superline; and

sending a region snoop request to acquire ownership of the first superline when the agent does not have ownership of the first superline.

14. The method as in claim 13, wherein the agent is a central processing unit.

15. The method as in claim 14, wherein reading an entry for the first superline from the on-die superline directory table cache includes reading an ownership bit associated with the agent.

16. The method as in claim 14, wherein determining if the agent has ownership of a first superline includes reading an entry for the first superline from a superline directory table in memory when the entry for the first superline is not stored in the on-die superline directory table cache, wherein reading the entry for the first superline includes reading an ownership bit associated with the agent.

17. The method as in claim 13, wherein the agent is a general-purpose graphics processing unit.

18. The method as in claim 17, wherein determining if the agent has ownership of a first superline includes reading an entry for the first superline from a superline ownership table within memory of the general-purpose graphics processing unit.

19. A heterogeneous data processing system comprising:

a general-purpose processor including a first cache memory and a first coherency module; and

a general-purpose graphics processor including a second cache memory and a second coherency module, wherein the first coherency module and the second coherency module enable heterogeneous coherency between the first cache memory and the second cache memory, the heterogeneous coherency enabled at multiple cache line granularity, wherein data storage for the first cache memory is managed at cache line granularity and coherence for shared virtual memory cached by the first cache memory and the second cache memory is managed at superline granularity.

20. The heterogeneous data processing system as in claim 19, additionally including a first memory module to store a superline directory table, the superline directory table to track ownership for each superline owned by the general-purpose processor and the general-purpose graphics processor, wherein each superline is an address region that spans multiple cache lines of the first cache memory and the second cache memory.