AMPLIFIER AND SEMICONDUCTOR APPARATUS USING THE SAME

• US 20180294784A1
• Filed: 08/03/2017
• Published: 10/11/2018
• Est. Priority Date: 04/10/2017
• Status: Active Application

• Current Assignee: SK Hynix Inc.
• Original Assignee: SK Hynix Inc.
• Inventors: KIM, Dong Hyun, CHOI, Eun Ji, JEONG, Yo Han, KANG, Soon Ku, KANG, Woo Jin, SHON, Kwan Su, LEE, Hyun Bae, HWANG, Tae Jin
• Granted Patent: US 10,284,156 B2
• Time in Patent Office: Days
• CPC Class Codes: G05F 1/565 sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor G05F1/563 takes precedence
• CPC Class Codes: H03F 2200/453 Controlling being realised by adding a replica circuit or by using one among multiple identical circuits as a replica circuit
• CPC Class Codes: H03F 2203/45008 the addition of two signals being made by a resistor addition circuit for producing the common mode signal
• CPC Class Codes: H03F 2203/45418 the CMCL comprising a resistor addition circuit
• CPC Class Codes: H03F 3/45076 characterised by the way of implementation of the active amplifying circuit in the differential amplifier
• CPC Class Codes: H03F 3/45183 Long tailed pairs H03F3/4521, H03F3/45237 take precedence
• CPC Class Codes: H03F 3/45488 by using feedback means H03F3/4578 takes precedence
• CPC Class Codes: H03F 3/4565 Controlling the common source circuit of the differential amplifier
• CPC Class Codes: H03F 3/45748 by using a feedback circuit
• CPC Class Codes: H03M 1/00 Analogue/digital conversion; Digital/analogue conversion conversion of analogue values to or from differential modulation H03M3/00

Abstract

An amplifier may include a differential pair circuit configured to generate an output signal according to a first input signal and a second input signal, a plurality of current sinks coupled between a ground terminal and the differential pair circuit, and a feedback circuit configured to sense a level of the output signal and generate a feedback signal. At least one of the plurality of current sinks is controlled according to the feedback signal.

Claims

1. An amplifier comprising:

a differential pair circuit configured to generate an output signal according to a first input signal and a second input signal;

a plurality of current sinks coupled between a ground terminal and the differential pair circuit; and

a feedback circuit configured to sense a level of the output signal and generate a feedback signal,

wherein at least one of the plurality of current sinks is controlled according to the feedback signal.

2. The amplifier according to claim 1, wherein any one of the plurality of current sinks is controlled according to a voltage having a fixed level when the amplifier is enabled.

3. The amplifier according to claim 1, wherein the plurality of current sinks are configured to have different current driving forces.

4. The amplifier according to claim 1, further comprising a plurality of loads coupled between a power supply terminal and the differential pair circuit.

5. The amplifier according to claim 4, wherein at least one of the plurality of loads is controlled according to the feedback signal

6. The amplifier according to claim 4, wherein the plurality of loads are configured to have different current driving forces.

7. The amplifier according to claim 1,

wherein any one of the first input signal and the second input signal is a reference voltage, and

wherein the feedback circuit includes a distribution resistance and is configured to generate the feedback signal according to a distribution voltage formed by distributing a voltage level of the output signal using the distribution resistance.

8. The amplifier according to claim 1,

wherein the first input signal and the second input signal are differential input signals having opposite phases, and

wherein the feedback circuit is a replica circuit formed by replicating the differential pair circuit and the plurality of loads, and is configured to generate the feedback signal according to an output voltage of the replica circuit.

9. The amplifier according to claim 8, wherein the feedback circuit further comprises an operational amplifier configured to generate the feedback signal according to a bias voltage and an output of the replica circuit.

10. The amplifier according to claim 1, further comprising

an analog-digital converter configured to generate a code signal by converting the feedback signal into a digital signal,

wherein at least one of the plurality of current sinks is controlled according to the code signal.

11. A semiconductor apparatus comprising:

a plurality of data input/output terminals;

a plurality of buffers coupled to the respective data input/output terminals; and

a feedback circuit configured to sense a level of any one output signal of the plurality of buffers and generate a feedback signal,

wherein at least one of a plurality of current sinks of each of the plurality of buffers is controlled according to the feedback signal.

12. The semiconductor apparatus according to claim 11, wherein the plurality of buffers comprise:

a differential pair circuit configured to generate an output signal according to an input signal inputted through the plurality of data input/output terminals; and

the plurality of current sinks coupled between a ground terminal and the differential pair circuit.

13. The semiconductor apparatus according to claim 12, wherein any one of the plurality of current sinks is controlled according to a voltage having a fixed level when any one of the plurality of buffers is enabled, and the other current sinks are controlled according to the feedback signal.

14. The semiconductor apparatus according to claim 11, wherein the feedback circuit is a replica circuit formed by replicating any one of the plurality of buffers and is configured to generate the feedback signal according to an output voltage of the replica circuit and provide the feedback signal to the plurality of buffers in common.

15. The semiconductor apparatus according to claim 14, wherein the feedback circuit further comprises an operational amplifier configured to generate the feedback signal by amplifying an output voltage of the replica circuit according to a bias voltage.

16. The semiconductor apparatus according to claim 11,

wherein the feedback circuit directly receives each of the output signals of the plurality of buffers, and

wherein the feedback circuit comprises a plurality of operational amplifiers configured to generate a plurality of feedback signals by amplifying respective output signals of the plurality of buffers according to a bias voltage.

17. A semiconductor device comprising:

a plurality of data input/output terminals;

a plurality of buffers coupled to the respective data input/output terminals; and

a feedback circuit configured to sense levels of respective output signals of the plurality of buffers and generate a plurality of feedback signals,

wherein at least one of a plurality of current sinks of each of the plurality of buffers is controlled according to any one of the plurality of feedback signals.

18. The semiconductor apparatus according to claim 17, wherein the plurality of buffers comprise:

a differential pair circuit configured to generate an output signal according to an input signal inputted through the plurality of data input/output terminals; and

the plurality of current sinks coupled between a ground terminal and the differential pair circuit.

19. The semiconductor apparatus according to claim 17, wherein any one of the plurality of current sinks is controlled according to a voltage having a fixed level when the plurality of buffers are enabled, and the other current sinks are controlled according to any one of the plurality of feedback signals.

20. The semiconductor apparatus according to claim 17,

wherein the feedback circuit directly receives each of output signals of the plurality of buffers, and

wherein the feedback circuit comprises a plurality of operational amplifiers configured to generate a plurality of feedback signals by amplifying respective output signals of the plurality of buffers according to a bias voltage.