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VMIN RETENTION DETECTOR APPARATUS AND METHOD

  • US 20180299506A1
  • Filed: 06/18/2018
  • Published: 10/18/2018
  • Est. Priority Date: 03/16/2016
  • Status: Active Grant
First Claim
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1. An apparatus comprising:

  • a combinational logic to provide a data on a data node;

    a multiplexer coupled to the data node and one of a supply node or a ground node, the multiplexer having an output node;

    a sequential logic having a data input, an output, and a clock input, wherein the output node of the multiplexer is coupled to the data input; and

    a compare logic having a first input coupled to the data input, and a second input coupled to the output of the sequential logic, wherein the compare logic is to detect a Vmin threshold of the sequential logic during a test mode.

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