VMIN RETENTION DETECTOR APPARATUS AND METHOD

• US 20180299506A1
• Filed: 06/18/2018
• Published: 10/18/2018
• Est. Priority Date: 03/16/2016
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Honkote, Vinayak, Vangal, Sriram R.
• Granted Patent: US 10,451,675 B2
• Time in Patent Office: Days
• CPC Class Codes: G01R 31/31703 Comparison aspects, e.g. signature analysis, comparators concerning scan tests G01R31/318566; concerning testers G01R31/3193
• CPC Class Codes: G01R 31/31727 Clock circuits aspects, e.g. test clock circuit details, timing aspects for signal generation, circuits for testing clocks G01R31/31725 takes precedence; concerning scan test G01R31/318552, for tester hardware G01R31/31922
• CPC Class Codes: G01R 31/3173 Marginal testing
• CPC Class Codes: G06F 1/26 Power supply means, e.g. regulation thereof for memories G11C
• CPC Class Codes: G06F 1/28 Supervision thereof, e.g. detecting power-supply failure by out of limits supervision
• CPC Class Codes: G06F 1/305 in the event of power-supply fluctuations
• CPC Class Codes: G06F 1/3206 Monitoring of events, devices or parameters that trigger a change in power modality
• CPC Class Codes: G06F 1/3296 by lowering the supply or operating voltage
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Described is an apparatus which comprises: a state detector which is operable to detect logic states of zero and one in response to a clock edge; and an error detector coupled to the state detector, wherein the error detector is to detect an error in the detected logic states.

Claims

1. An apparatus comprising:

a combinational logic to provide a data on a data node;

a multiplexer coupled to the data node and one of a supply node or a ground node, the multiplexer having an output node;

a sequential logic having a data input, an output, and a clock input, wherein the output node of the multiplexer is coupled to the data input; and

a compare logic having a first input coupled to the data input, and a second input coupled to the output of the sequential logic, wherein the compare logic is to detect a V_min threshold of the sequential logic during a test mode.

2. The apparatus of claim 1, wherein the multiplexer is a first multiplexer, wherein the apparatus comprises a second multiplexer coupled to a test clock node and a regular clock node, wherein the second multiplexer has an output coupled to the clock input of the sequential logic.

3. The apparatus of claim 2, wherein the second multiplexer is to provide a test clock on the test clock node to the clock input during the test mode.

4. The apparatus of claim 2, wherein the second multiplexer is to provide a regular clock on the regular clock node to the clock input during a normal mode or a non-test mode.

5. The apparatus of claim 1, wherein the sequential logic has a tunable load coupled to one of its nodes.

6. The apparatus of claim 1, wherein the compare logic is an exclusive-OR gate.

7. The apparatus of claim 2, wherein the first and second multiplexers are controllable by signal indicating the test mode.

8. The apparatus of claim 1, wherein the data node of the combinational logic is coupled to a first input of the multiplexer, and wherein the multiplexer has a second input coupled to one of a power supply node or a ground node.

9. The apparatus of claim 1, wherein the combinational logic is a first combinational logic, wherein multiplexer is a first multiplexer, wherein the sequential logic is a first sequential logic, wherein the compare logic is a first compare logic, wherein the apparatus comprises:

a second combinational logic to provide a second data on a second data node;

a third multiplexer coupled to the second data node and one of the supply node or the ground node, the third multiplexer having an output node;

a second sequential logic having a data input, an output, and a clock input, wherein the output node of the third multiplexer is coupled to the data input; and

a second compare logic having a first input coupled to the data input, and a second input coupled to the output of the second sequential logic, wherein the second compare logic is to detect a V_min threshold of the sequential logic during the test mode.

10. The apparatus of claim 9 comprises a summer to sum outputs of the first and second compare logics.

11. The apparatus of claim 10 comprises a power management unit to receive an output of the summer.

12. The apparatus of claim 9, wherein outputs of the first and second compare logics are merged by a merging circuitry to generate a merged output.

13. The apparatus of claim 12, comprises a power management unit to receive the merged output.

14. The apparatus of claim 12, wherein the merging circuitry comprise a OR gate.

15. An apparatus comprising:

a logic to provide a data on a data node;

a selector coupled to the data node and one of a supply node or a ground node, the selector having an output node;

a flip-flop having a data input, an output, and a clock input, wherein the output node of the selector is coupled to the data input; and

a comparator having a first input coupled to the data input, and a second input coupled to the output of the sequential logic.

16. The apparatus of claim 15, wherein the selector is a first selector, wherein the apparatus comprises a second selector coupled to a test clock node and a regular clock node, wherein the second selector has an output coupled to the clock input of the flip-flop.

17. The apparatus of claim 15, wherein the comparator comprises one of:

an exclusive-OR (XOR) gate;

or

an exclusive-NOR (XNOR) gate.

18. The apparatus of claim 16, wherein the second selector is to provide a test clock on the test clock node to the clock input during the test mode.

19. A system comprising:

a memory,

a processor coupled to the memory, the processor including a V_min retention detector apparatus which comprises;

a logic to provide a data on a data node;

a selector coupled to the data node and one of a supply node or a ground node, the selector having an output node;

a flip-flop having a data input, an output, and a clock input, wherein the output node of the selector is coupled to the data input; and

a comparator having a first input coupled to the data input, and a second input coupled to the output of the sequential logic; and

a wireless interface to allow the processor to communicate with another device.

20. The system of claim 19, wherein the selector is a first selector, wherein the apparatus comprises a second selector coupled to a test clock node and a regular clock node, wherein the second selector has an output coupled to the clock input of the flip-flop.