BOOSTING LOCAL MEMORY PERFORMANCE IN PROCESSOR GRAPHICS

• US 20180300139A1
• Filed: 10/29/2015
• Published: 10/18/2018
• Est. Priority Date: 10/29/2015
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Que, Can K.
• Granted Patent: US 10,768,935 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 12/0804 with main memory updating G06F12/0806 takes precedence
• CPC Class Codes: G06F 2212/1016 Performance improvement
• CPC Class Codes: G06F 2212/1024 Latency reduction
• CPC Class Codes: G06F 9/30138 Extension of register space, e.g. register cache
• CPC Class Codes: G06F 9/3867 using instruction pipelines
• CPC Class Codes: G06F 9/3887 controlled by a single instruction for multiple data lanes [SIMD]
• CPC Class Codes: G06F 9/522 Barrier synchronisation
• CPC Class Codes: G06T 1/20 Processor architectures; Processor configuration, e.g. pipelining
• CPC Class Codes: G06T 1/60 Memory management
• CPC Class Codes: G06T 19/00 Manipulating 3D models or images for computer graphics

Abstract

In some cases, processor graphics with a slower local memory can compensate by using another memory in place of the lowest level or L3 cache. For example, in some processors, there is a large register space that can be used for the local memory function by allocating the local memory within those registers. Also, since the registers do not operate with barriers, barriers can be simulated by letting one execution unit thread execute more SIMD instructions. For example, one execution thread may simulate a whole work-group in the OpenCL API.

Claims

1. A method comprising:

using register files as local memory in place of a lowest level cache.

2. The method of claim 1 including also using a lowest level cache as local memory when said register files have insufficient storage space.

3. The method of claim 1 including simulating a barrier by allowing one execution unit thread to execute more single instruction multiple data instructions.

4. The method of claim 3 including using one thread to simulate an entire work-group.

5. The method of claim 1 including using said register files to implement an OpenCL local memory.

6. The method of claim 1 including transforming a non-aligned write using a permutation.

7. The method of claim 1 including transforming a non-aligned write to use only one hardware instruction for permutation multiplication.

8. The method of claim 6 including generating log (k−

1) instructions to transform source registers.

9. The method of claim 8 including determining whether a kernel should cache a permutated pattern.

10. The method of claim 9 wherein determining including determining how often a write pattern occurs in a kernel.

11. One or more non-transitory computer readable media storing instructions to perform a sequence comprising:

using register files as local memory in place of a lowest level cache.

12. The media of claim 11 including also using a lowest level cache as local memory when said register files have insufficient storage space.

13. The media of claim 11 including simulating a barrier by allowing one execution unit thread to execute more single instruction multiple data instructions.

14. The media of claim 13 including using one thread to simulate an entire work-group.

15. The media of claim 11 including using said register files to implement an OpenCL local memory.

16. The media of claim 11 including transforming a non-aligned write using a permutation.

17. The media of claim 11 including transforming a non-aligned write to use only one hardware instruction for permutation multiplication.

18. The media of claim 16 including generating log (k−

1) instructions to transform source registers.

19. The media of claim 18 including determining whether a kernel should cache a permutated pattern.

20. The media of claim 19 wherein determining including determining how often a write pattern occurs in a kernel.

21. An apparatus comprising:

a processor to use register files as local memory in place of a lowest level cache; and

a storage coupled to said processor.

22. The apparatus of claim 21, said processor to use a lowest level cache as local memory when said register files have insufficient storage space.

23. The apparatus of claim 21, said processor to simulate a barrier by allowing one execution unit thread to execute more single instruction multiple data instructions.

24. The apparatus of claim 23, said processor to use one thread to simulate an entire work-group.

25. The apparatus of claim 21, said processor to use said register files to implement an OpenCL local memory.

26. The apparatus of claim 21, said processor to transform a non-aligned write using a permutation.

27. The apparatus of claim 21, said processor to transform a non-aligned write to use only one hardware instruction for permutation multiplication.

28. The apparatus of claim 26, said processor to generate log (k−

1) instructions to transform source registers.

29. The apparatus of claim 28, said processor to determine whether a kernel should cache a permutated pattern.

30. The apparatus of claim 29, said processor to determine how often a write pattern occurs in a kernel.