BIT REORDERING FOR MEMORY DEVICES
First Claim
Patent Images
1. A memory device, comprising:
- a plurality of non-volatile memory elements configured to process a plurality of read and/or write operations; and
a controller connected to the plurality of non-volatile memory elements via one or more buses, wherein each of the one or more buses is configured to connect at least two of the plurality of non-volatile memory elements to the controller;
wherein the controller is configured to;
receive an input bit sequence including a plurality of bits with a first bit order, wherein the controller writes the input bit sequence to one of the plurality of non-volatile memory elements;
identify a physical location of the non-volatile memory element in the memory device;
determine a correspondence between the first bit order and a second bit order based on the physical location; and
generate an output bit sequence including the plurality of bits with the second bit order based on the correspondence
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Abstract
The present disclosure discloses a memory device including a controller for bit reordering. The controller receives an input bit sequence including a plurality of bits with a first bit order. The controller identifies a physical location of a non-volatile memory element in the memory device and determines a correspondence between the first bit order and a second bit order based on the physical location. The controller generates an output bit sequence including the plurality of bits with the second bit order based on the correspondence.
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Citations
28 Claims
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1. A memory device, comprising:
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a plurality of non-volatile memory elements configured to process a plurality of read and/or write operations; and a controller connected to the plurality of non-volatile memory elements via one or more buses, wherein each of the one or more buses is configured to connect at least two of the plurality of non-volatile memory elements to the controller; wherein the controller is configured to; receive an input bit sequence including a plurality of bits with a first bit order, wherein the controller writes the input bit sequence to one of the plurality of non-volatile memory elements; identify a physical location of the non-volatile memory element in the memory device; determine a correspondence between the first bit order and a second bit order based on the physical location; and generate an output bit sequence including the plurality of bits with the second bit order based on the correspondence - View Dependent Claims (2, 3, 4)
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5. A memory device, comprising:
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a plurality of processing means configured to process a plurality of read and/or write operations; and a controlling means connected to the plurality of processing means via one or more buses, wherein each of the one or more buses is configured to connect at least two of the plurality of processing means to the controlling means; wherein the controlling means is configured to; receive an input bit sequence including a plurality of bits with a first bit order, wherein the controlling means writes the input bit sequence to one of the plurality of processing means; identify a physical location of the processing means in the memory device; determine a correspondence between the first bit order and a second bit order based on the physical location; and generate an output bit sequence including the plurality of bits with the second bit order based on the correspondence. - View Dependent Claims (6, 7, 8, 9, 10)
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11. A memory device, comprising:
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a plurality of non-volatile memory elements configured to process a plurality of read and/or write operations; and a controller connected to the plurality of non-volatile memory elements via one or more buses, wherein each of the one or more buses is configured to connect at least two of the plurality of non-volatile memory elements to the controller; wherein the controller is configured to; receive an input bit sequence including a plurality of bits with a first bit order, wherein the controller reads the input bit sequence from one of the plurality of non-volatile memory elements; identify a physical location of the non-volatile memory element in the memory device; determine a correspondence between the first bit order and a second bit order based on the physical location; generate an output bit sequence including the plurality of bits with the second bit order based on the correspondence; and transmit the output bit sequence to a processor in the controller for processing. - View Dependent Claims (12, 13, 14)
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15. A memory device, comprising:
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a plurality of processing means configured to process a plurality of read and/or write operations; and a controlling means connected to the plurality of processing means via one or more buses, wherein each of the one or more buses is configured to connect at least two of the plurality of processing means to the controlling means; wherein the controlling means is configured to; receive an input bit sequence including a plurality of bits with a first bit order, wherein the controlling means reads the input bit sequence from one of the plurality of processing means; identify a physical location of the processing means in the memory device; determine a correspondence between the first bit order and a second bit order based on the physical location; generate an output bit sequence including the plurality of bits with the second bit order based on the correspondence; and transmit the output bit sequence to a processor in the controlling means for processing. - View Dependent Claims (16, 17, 18, 19, 20)
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21. A method, comprising:
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receiving, by a controller in a memory device, an input bit sequence including a plurality of bits with a first bit order, wherein the controller writes the input bit sequence to one of a plurality of non-volatile memory elements in the memory device; identifying a physical location of the non-volatile memory element in the memory device; determining a correspondence between the first bit order and a second bit order based on the physical location; and generating an output bit sequence including the plurality of bits with the second bit order based on the correspondence. - View Dependent Claims (22, 23, 24)
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25. A method, comprising:
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receiving, by a controller in a memory device, an input bit sequence including a plurality of bits with a first bit order, wherein the controller reads the input bit sequence from one of a plurality of non-volatile memory elements in the memory device; identifying a physical location of the non-volatile memory element in the memory device; determining a correspondence between the first bit order and a second bit order based on the physical location; generating an output bit sequence including the plurality of bits with the second bit order based on the correspondence; and transmitting the output bit sequence to a processor in the controller for processing. - View Dependent Claims (26, 27, 28)
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Specification