LOW POWER READ OPERATION FOR PROGRAMMABLE RESISTIVE MEMORIES
First Claim
1. A programmable resistive memory, comprises:
- a plurality of programmable resistive device (PRD) cells; and
a time-based sensing circuit including at least;
a capacitor selectably connected to a voltage source line;
a selector controlled by a control signal, the selector having a first end and a second end, the second end being coupled to a first conductive line;
a programmable resistive element (PRE) having a first end coupled to the capacitor and a second end coupled to the first end of the selector; and
a comparator coupled to the first end of the PRE,wherein the time-based sensing circuit using different discharge time to determine resistance of the PRE.
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Abstract
A programmable resistive memory has a plurality of programmable resistive devices (PRD) and at least one sensing circuit. The at least one of the programmable resistive device can include at least one programmable resistive element (PRE). The sensing circuit can include one PRD unit and a reference unit. Each unit has at least one capacitor to charge to a second supply voltage line and to discharge to the first supply voltage line through the PRE and the reference element, respectively. The capacitors are also coupled to comparators to monitor discharging voltages with respect to a reference voltage. By comparing the time difference when the comparators change their outputs, the magnitude of the PRE resistance with respect to the reference element resistance can be determined and converted into logic states.
53 Citations
19 Claims
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1. A programmable resistive memory, comprises:
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a plurality of programmable resistive device (PRD) cells; and a time-based sensing circuit including at least; a capacitor selectably connected to a voltage source line; a selector controlled by a control signal, the selector having a first end and a second end, the second end being coupled to a first conductive line; a programmable resistive element (PRE) having a first end coupled to the capacitor and a second end coupled to the first end of the selector; and a comparator coupled to the first end of the PRE, wherein the time-based sensing circuit using different discharge time to determine resistance of the PRE. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. An electronic system, comprises:
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a processor; and a programmable resistive memory operatively connected to the processor, the programmable resistive memory includes at least a plurality of programmable resistive device (PRD) cells for providing data storage, each of the programmable resistive device cells comprising; a programmable resistive element (PRE) coupled to a first supply voltage line through a selector with an enable signal; and a time-base sensing circuit coupled to at least one PRD cell unit and a reference unit having PRE and reference resistor, respectively;
each unit has at least one capacitor that can be charged to a second supply voltage line and discharged through PRE and reference resistor, respectively, to the first supply voltage line;
each unit has at least one comparators coupled to the capacitors to change output when the voltage discharged to a reference voltage.wherein the capacitors in both units are charged to the second supply voltage approximately and discharged to the first supply voltage line by turning on the enable signal at the same time, and wherein the PRE resistance can be converted into logic state by the time difference of the comparators changing outputs. - View Dependent Claims (10, 11, 12, 13, 14, 15)
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16. A method for providing a programmable resistive memory including a plurality of programmable resistive device cells, at least one of the programmable resistive device cells including at least a programmable resistive element and a capacitor, the method comprising:
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charging the capacitor; ceasing the charging; subsequently coupling the programmable resistive element to the capacitor; monitoring a discharge rate of the capacitor while the programmable resistance element remains coupled to the capacitor; determining a resistance value of the programmable resistive element based on the monitoring of the discharge rate; and determining a logic state for the at least one of the programmable resistive device cells based in the determined resistance value of the programmable resistive element. - View Dependent Claims (17, 18)
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19. A method for providing a programmable resistive memory, comprising:
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providing a plurality of programmable resistive device cells, at least one of the programmable resistive device cells include at least (i) a programmable resistive element coupled to a first supply voltage line through a selector with an enable signal; and
(ii) a time-base sensing circuit coupled to at least one PRD cell unit and a reference unit having PRE and a reference resistor, respectively;
each unit has at least one capacitor that can be charged via a second supply voltage line and discharged through PRE and reference resistor, respectively, via the first supply voltage line;
each unit has at least one comparator coupled to the respective capacitors to change output when the voltage discharged is compared to a reference voltage;turning on the enable signal of the PRD unit and reference unit, after the capacitors are charged to the second supply voltage approximately, to discharge the capacitors through the PRE and reference element respectively; and converting the PRE resistance into logic states by the time difference of the comparator output changes.
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Specification