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LOW POWER READ OPERATION FOR PROGRAMMABLE RESISTIVE MEMORIES

  • US 20180301198A1
  • Filed: 04/14/2018
  • Published: 10/18/2018
  • Est. Priority Date: 04/14/2017
  • Status: Active Grant
First Claim
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1. A programmable resistive memory, comprises:

  • a plurality of programmable resistive device (PRD) cells; and

    a time-based sensing circuit including at least;

    a capacitor selectably connected to a voltage source line;

    a selector controlled by a control signal, the selector having a first end and a second end, the second end being coupled to a first conductive line;

    a programmable resistive element (PRE) having a first end coupled to the capacitor and a second end coupled to the first end of the selector; and

    a comparator coupled to the first end of the PRE,wherein the time-based sensing circuit using different discharge time to determine resistance of the PRE.

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