METHOD OF SELECTIVE VERTICAL GROWTH OF A DIELECTRIC MATERIAL ON A DIELECTRIC SUBSTRATE

• US 20180301335A1
• Filed: 04/12/2018
• Published: 10/18/2018
• Est. Priority Date: 04/12/2017
• Status: Active Grant

• Current Assignee: Tokyo Electron Limited
• Original Assignee: Tokyo Electron Limited
• Inventors: Tapily, Kandabara N., Matsumoto, Takashi, Kashiwagi, Yusaku, Leusink, Gerrit J.
• Granted Patent: US 10,453,681 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/02164 the material being a silicon oxide, e.g. SiO2
• CPC Class Codes: H01L 21/02175 characterised by the metal H01L21/02197 takes precedence
• CPC Class Codes: H01L 21/02216 the compound being a molecule comprising at least one silicon-oxygen bond and the compound having hydrogen or an organic group attached to the silicon or oxygen, e.g. a siloxane
• CPC Class Codes: H01L 21/02277 the reactions being activated by other means than plasma or thermal, e.g. photo-CVD
• CPC Class Codes: H01L 21/0228 deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
• CPC Class Codes: H01L 21/02491 Conductive materials
• CPC Class Codes: H01L 21/02527 Carbon, e.g. diamond-like carbon
• CPC Class Codes: H01L 21/0262 Reduction or decomposition of gaseous compounds, e.g. CVD
• CPC Class Codes: H01L 21/02639 Preparation of substrate for selective deposition
• CPC Class Codes: H01L 21/02645 Seed materials
• CPC Class Codes: H01L 21/32 using masks
• CPC Class Codes: H01L 21/321 After treatment
• CPC Class Codes: H01L 21/76801 characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
• CPC Class Codes: H01L 21/76816 Aspects relating to the layout of the pattern or to the size of vias or trenches layout of the interconnections per se H01L23/528; CAD of ICs G06F30/00
• CPC Class Codes: H01L 21/76829 characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665

Abstract

Embodiments of the invention describe methods for selective vertical growth of dielectric material on a dielectric substrate. According to one embodiment, the method includes providing a planarized substrate containing a first material having a recessed feature that is filled with a second material, selectively depositing a graphene layer on the second material relative to the first material, selectively depositing a SiO₂ film on the first material relative to the graphene layer, and removing the graphene layer from the substrate. According to one embodiment, the first material includes a dielectric material and the second material includes a metal layer.

Claims

1. A substrate processing method, comprising:

providing a planarized substrate containing a first material having a recessed feature that is filled with a second material;

selectively depositing a graphene layer on the second material relative to the first material;

selectively depositing a SiO₂ film on the first material relative to the graphene layer; and

removing the graphene layer from the substrate.

2. The method of claim 1, further comprising

removing the second material from the recessed feature.

3. The method of claim 1, wherein the selectively depositing a SiO₂ film includes

coating the first material with a metal-containing catalyst layer;

and

in the absence of any oxidizing and hydrolyzing agent, and in the absence of a plasma, exposing the substrate at a substrate temperature of approximately 150°

C. or less, to a process gas containing a silanol gas.

4. The method claim 3, further comprising

repeating the coating and exposing at least once to increase the thickness of the SiO₂ film on the first material.

5. The method of claim 3, wherein the metal-containing catalyst layer contains aluminum, titanium, or a combination thereof.

6. The method of claim 3, wherein the metal-containing catalyst layer is selected from the group consisting of Al, Al₂O₃, AlN, AlON, an Al-containing precursor, Al-alloys, CuAl, TiAlN, TaAlN, Ti, TiAlC, TiO₂, TiON, TiN, a Ti-containing precursor, Ti-alloys, and combinations thereof.

7. The method of claim 3, wherein the coating includes exposing the substrate to AlMe₃ gas.

8. The method of claim 3, wherein the silanol gas is selected from the group consisting of tris(tert-pentoxy) silanol, tris(tert-butoxy) silanol, and bis(tert-butoxy)(isopropoxy) silanol.

9. The method of claim 1, wherein the first material includes a dielectric material and the second material includes a metal layer.

10. The method of claim 9, wherein the metal layer is selected from the group consisting of Ni, Cu, and Ru.

11. The method of claim 1, wherein the selectively depositing the SiO₂ film forms a second recessed feature that is aligned with the recessed feature that is filled with the second material, the method further including

filling the second recessed feature with a third material.

12. The method of claim 11, wherein the third material includes a metal layer selected from Ni, Cu, and Ru.

13. The method of claim 11, further including

selectively depositing an additional graphene layer on the third material relative to the SiO₂ film;

selectively depositing an additional SiO₂ film on the SiO₂ film relative to the additional graphene layer;

removing the additional graphene layer from the third material.

14. The method of claim 13, further comprising

removing the third material from the substrate.

15. The method of claim 13, further comprising

removing the second and third materials from the substrate.

16. The method of claim 13, wherein the selectively depositing the additional SiO₂ film includes

coating the SiO₂ film with a metal-containing catalyst layer;

and

in the absence of any oxidizing and hydrolyzing agent, and in the absence of a plasma, exposing the substrate at a substrate temperature of approximately 150°

C. or less, to a process gas containing a silanol gas.

17. The method claim 16, further comprising

repeating the coating and exposing at least once to increase the thickness of the additional SiO₂ film on the SiO₂ film.

18. The method of claim 16, wherein the metal-containing catalyst layer contains aluminum, titanium, or a combination thereof.

19. The method of claim 16, wherein the metal-containing catalyst layer is selected from the group consisting of Al, Al₂O₃, AN, AlON, an Al-containing precursor, Al-alloys, CuAl, TiAlN, TaAlN, Ti, TiAlC, TiO₂, TiON, TiN, a Ti-containing precursor, Ti-alloys, and combinations thereof.

20. The method of claim 16, wherein the silanol gas is selected from the group consisting of tris(tert-pentoxy) silanol, tris(tert-butoxy) silanol, and bis(tert-butoxy)(isopropoxy) silanol.