POWER SWITCH AND SEMICONDUCTOR DEVICE THEREOF

• US 20180302084A1
• Filed: 03/22/2018
• Published: 10/18/2018
• Est. Priority Date: 04/18/2017
• Status: Active Grant

• Current Assignee: uPI Semiconductor Corporation
• Original Assignee: uPI Semiconductor Corporation
• Inventors: WU, Chia-Long
• Granted Patent: US 10,461,741 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/823493 with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/36 characterised by the concentration or distribution of impurities in the bulk material within semiconductor regions H01L29/06
• CPC Class Codes: H03K 17/6871 the output circuit comprising more than one controlled field-effect transistor
• CPC Class Codes: H03K 2217/0018 Special modifications or use of the back gate voltage of a FET

Abstract

A power switch and a semiconductor device thereof are disclosed. The power switch device includes a first transistor cell, a second transistor cell, a body region and a conductive layer. The first transistor cell includes a first electrode. The second transistor cell includes a second electrode. The body region is disposed between the first transistor cell and the second transistor cell. The conductive layer is electrically connected with the body region, the first electrode and the second electrode respectively.

Claims

1. A power switch, comprising:

a first transistor cell comprising a first electrode;

a second transistor cell comprising a second electrode;

a body region disposed between the first transistor cell and the second transistor cell; and

a conductive layer electrically connected with the body region, the first electrode and the second electrode respectively.

2. The power switch of claim 1, wherein the body region is adjacent to the first electrode and the second electrode respectively.

3. The power switch of claim 1, wherein the first electrode is a first drain electrode of the first transistor cell and the second electrode is a second source electrode of the second transistor cell.

4. The power switch of claim 3, wherein the first transistor cell further comprises a first source electrode and a first gate electrode, and the first source electrode is coupled to a first voltage and the first gate electrode is controlled by a second voltage;

the second transistor cell further comprises a second drain electrode and a second gate electrode, and the second drain electrode is coupled to the second voltage and the second gate electrode is controlled by the first voltage.

5. The power switch of claim 1, wherein when the power switch is turned on, the first transistor cell is conducted but the second transistor cell is not conducted, and a base electrode voltage of the body region is maintained at a first voltage;

when the power switch is turned off, the second transistor cell is conducted but the first transistor cell is not conducted, and the base electrode voltage is maintained at a second voltage.

6. The power switch of claim 1, wherein a base electrode voltage of the body region is selectively maintained at a lower one of a first voltage and a second voltage.

7. A semiconductor device of a power switch, comprising:

a substrate having a first conductive material;

a first well, disposed on the substrate, having a second conductive material;

a second well, disposed on the first well, having the first conductive material;

a first transistor cell, disposed in the second well, having a first electrode;

a second transistor cell, disposed in the second well, having a second electrode; and

a metal layer, disposed on a surface of the semiconductor device and electrically connected with the first electrode, the second electrode and the second well respectively.

8. The semiconductor device of claim 7, further comprising:

a first doped region, disposed in the second well and electrically connected with the metal layer, having the first conductive material.

9. The semiconductor device of claim 8, wherein the first doped region is disposed between the first transistor cell and the second transistor cell.

10. The semiconductor device of claim 8, wherein a doping concentration of the first conductive material in the first doped region is higher than that of the first conductive material in the second well and the substrate.

11. The semiconductor device of claim 7, further comprising:

a second doped region, disposed in the second well and electrically connected with the first electrode or the second electrode, having the second conductive material.

12. The semiconductor device of claim 7, wherein the first well is coupled to an operating voltage.

13. The semiconductor device of claim 7, wherein the substrate is coupled to a ground voltage.