SMART MEMORY BUFFERS

• US 20180307420A1
• Filed: 06/18/2018
• Published: 10/25/2018
• Est. Priority Date: 10/30/2012
• Status: Active Grant

• Current Assignee: Hewlett Packard Enterprise Development LP (Hewlett-Packard Enterprise Company)
• Original Assignee: Hewlett Packard Enterprise Development LP (Hewlett-Packard Enterprise Company)
• Inventors: Yoon, Doe Hyun, Muralimanohar, Naveen, Chang, Jichuan, Ranganathan, Parthasarathy
• Granted Patent: US 10,585,602 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 11/108 Parity data distribution in semiconductor storages, e.g. in SSD
• CPC Class Codes: G06F 2211/1054 Parity-fast hardware, i.e. dedicated fast hardware for RAID systems with parity
• CPC Class Codes: G06F 2211/1066 Parity-small-writes, i.e. improved small or partial write techniques in RAID systems
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/065 Replication mechanisms
• CPC Class Codes: G06F 3/0655 Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
• CPC Class Codes: G06F 3/0656 Data buffering arrangements
• CPC Class Codes: G06F 3/0665 at area level, e.g. provisioning of virtual or logical volumes
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays
• CPC Class Codes: G06F 3/0689 Disk arrays, e.g. RAID, JBOD

Abstract

An example method involves receiving, at a first memory node, data to be written at a memory location in the first memory node. The data is received from a device. At the first memory node, old data is read from the memory location, without sending the old data to the device. The data is written to the memory location. The data and the old data are sent from the first memory node to a second memory node to store parity information in the second memory node without the device determining the parity information. The parity information is based on the data stored in the first memory node.

Claims

1. A method to write data in a memory node, comprising:

receiving, at a first memory node, new data to be written at a memory location in the first memory node, the new data received from a device;

at the first memory node, reading old data from the memory location, without sending the old data to the device;

at the first memory node, writing the new data to the memory location; and

sending the new data and the old data from the first memory node to a second memory node to store parity information in the second memory node without the device determining the parity information, the parity information based at least on the new data stored in the first memory node.

2. A method as defined in claim 1, wherein the device is a processor, and the first memory node is in communication with the processor and the second memory node via a network interface.

3. A method as defined in claim 1, further comprising, after receiving the new data at the first memory node, not requiring further communications with the device to write the new data in the memory location and to send the new data and the old data from the first memory node to the second memory node.

4. A method as defined in claim 1, wherein the device is a third memory node in network communication with the first memory device, the data being forwarded data sourced by a processor in communication with the third memory node.

5. A method as defined in claim 1, further comprising, in response to a node-to-node copy request, sending the data stored at the memory location of the first memory node from the first memory node to a third memory node for writing to the third memory node.

6. A method as defined in claim 5, further comprising receiving the node-to-node copy request at the first memory node from the requesting device or another requesting device external from the first memory node.

7. A method as defined in claim 5, wherein the node-to-node copy request is an automatic event generated at the first memory node without intervention from an external device.

8. An apparatus to store data in a networked memory organization, comprising:

a plurality of dynamic random access memory modules; and

network interfaces on the dynamic random access memory modules to communicatively couple the dynamic random access memory modules, and to communicatively couple at least some of the dynamic random access memory modules to a processor to allow the processor to access data stored in any of the dynamic random access memory modules; and

logic circuits on respective ones of the dynamic random access memory modules to generate parity information to store in a distributed arrangement across the plurality of dynamic random access memory modules.

9. An apparatus as defined in claim 8, wherein the data and the parity is stored across the dynamic random access memory modules in a striped arrangement.

10. An apparatus as defined in claim 8, wherein the dynamic random access memory modules are mounted on a single printed circuit board.

11. An apparatus to read data comprising:

a processor; and

a plurality of memory nodes in communication with the processor and with one another, the processor to send a request for data to a first one of the memory nodes, the data stored in a distributed configuration in at least the first memory node and a second one of the memory nodes, the first memory node to retrieve a first portion of the data from a first memory location of the first memory node, the second memory node to retrieve a second portion of the data from a second memory location of the second memory node, and the second memory node to send the first and second portions of the data to the processor.

12. An apparatus as defined in claim 11, wherein the first and second memory nodes are solid state memory modules comprising at least one of dynamic random access memory or non-volatile memory.

13. An apparatus as defined in claim 11, wherein the first and second memory nodes are mounted on a single printed circuit board.

14. An apparatus as defined in claim 11, wherein the second memory node is to retrieve the second portion of the data after receiving the first portion of the data at the second memory node from the first memory node.

15. An apparatus as defined in claim 11, wherein the second memory node is to retrieve the second portion of the data without receiving a request for the second portion of the data directly from the processor.