DISPLAY PANEL, AND METHOD FOR DRIVING THE DISPLAY PANEL

• US 20180308417A1
• Filed: 06/25/2018
• Published: 10/25/2018
• Est. Priority Date: 04/09/2018
• Status: Active Grant

• Current Assignee: Xiamen Tianma Micro-Electronics Co., Ltd.
• Original Assignee: Xiamen Tianma Micro-Electronics Co., Ltd.
• Inventors: XIE, Huimin, LAN, Xuexin, WEN, Liang, ZHOU, Xiufeng, LI, Donghua, WU, Xiaoxiao
• Granted Patent: US 10,783,821 B2
• Time in Patent Office: Days
• CPC Class Codes: G09G 2300/0426 Layout of electrodes and connections
• CPC Class Codes: G09G 2310/0202 Addressing of scan or signal lines
• CPC Class Codes: G09G 2310/0232 Special driving of display border areas
• CPC Class Codes: G09G 2310/0267 Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
• CPC Class Codes: G09G 2310/0281 Arrangement of scan or data electrode driver circuits at the periphery of a panel not inherent to a split matrix structure
• CPC Class Codes: G09G 2310/08 Details of timing specific for flat panels, other than clock recovery
• CPC Class Codes: G09G 3/2096 Details of the interface to the display terminal specific for a flat panel suitable for both CRT and flat panel G09G5/006; specific for a CRT G09G1/167
• CPC Class Codes: G09G 3/3266 Details of drivers for scan electrodes
• CPC Class Codes: G09G 3/3677 suitable for active matrices only

Abstract

The disclosure provides a display panel and a method for driving the display panel. The display panel includes a display area and a peripheral area surrounding the display area, and the display area includes one first display area and at least one second display area. The design according to embodiments of the disclosure release enough space occupied by the peripheral area at one side of the at least one second display area far away from the first display area, thus increasing display area in desired direction and a screen-to-total face ratio.

Claims

1. A display panel, comprising:

a display area and a peripheral area surrounding the display area;

wherein the display area comprises one first display area and at least one second display area;

wherein the first display area comprises at least two first scan signal lines arranged along a first direction, wherein each of the at least two first scan signal lines has a first terminal and a second terminal in the first direction;

wherein each of the at least one second display area comprises at least two second scan signal lines arranged along the first direction, wherein each of the at least two second scan signal lines has a third terminal close to the peripheral area in the first direction;

wherein the first display area and the second display area are arranged along the first direction;

wherein the peripheral area comprises a plurality of cascaded first scan control circuits close to the first and second terminals of the at least two first scan signal lines, and a plurality of cascaded second scan control circuits close to the third terminals of the at least two second scan signal lines; and

wherein each of the at least two first scan signal lines is electrically connected to one of the plurality of cascaded first scan control circuits close to the first and second terminals alternately; and

wherein each of the at least two second scan signal lines is electrically connected to one of the plurality of cascaded second scan control circuits.

2. The display panel according to claim 1,

wherein each of the plurality of cascaded first scan control circuits and each of the plurality of cascaded second scan control circuits share a same structure;

wherein the display area comprises two second display areas;

wherein the peripheral area comprises a spacing area, a first peripheral area, a second peripheral area, and at least two third peripheral areas;

wherein the spacing area and the two second display areas are arranged on a same side of the first display area, and the spacing area is between the two second display areas;

wherein the first and second peripheral areas are on two opposite sides of the first display area, respectively;

wherein each of the at least two third peripheral areas is on one same side of each of the two second display areas farthest away from the spacing area;

wherein one of the at least two third peripheral areas and the first peripheral area are on one side of the display area, and another one of the at least two third peripheral areas and the second peripheral area are on another side of the display area;

wherein the plurality of cascaded first scan control circuits are in the first and second peripheral areas, and the plurality of cascaded second scan control circuits are in the at least two third peripheral areas.

3. The display panel according to claim 2, wherein the peripheral area further comprises a first group of clock signal lines and a second group of clock signal lines;

wherein the first group of clock signal lines are electrically connected to the plurality of cascaded first scan control circuits and the plurality of cascaded second scan control circuits on a side of the display area, respectively; and

wherein the second group of clock signal lines are electrically connected to the plurality of cascaded first scan control circuits and the plurality of cascaded second scan control circuits located on another side of the display area, respectively.

4. The display panel according to claim 3,

wherein in each second display area, two of the at least two second scan signal lines separated by another second scan signal line are electrically connected to one of the plurality of cascaded second scan control circuits;

and

wherein each of the first and second groups of clock signal lines comprises six clock signal lines.

5. The display panel according to claim 4,

wherein on one side of the display area, each of the plurality of cascaded first scan control circuits is electrically connected to a first clock signal line and a third clock signal line in the first group of clock signal lines, respectively;

wherein one of two adjacent second scan control circuits is electrically connected to the first clock signal line, the third clock signal line and a fifth clock signal line in the first group of clock signal lines, and wherein the other one of the two adjacent second scan control circuits is electrically connected to a second clock signal line, wherein a fourth clock signal line and a sixth clock signal line in the first group of clock signal lines;

wherein on another side of the display area, each of the plurality of cascaded first scan control circuits is electrically connected to a second clock signal line and a fourth clock signal line in the second group of clock signal lines, respectively;

wherein one of two adjacent second scan control circuits is electrically connected to a first clock signal line, a third clock signal line and a fifth clock signal line in the second group of clock signal lines, and the other one of the two adjacent second scan control circuits is electrically connected to the second clock signal line, wherein the fourth clock signal line and a sixth clock signal line in the second group of clock signal lines.

6. The display panel according to claim 3,

wherein in each of the two second display areas, two adjacent second scan signal lines are electrically connected to one of the second scan control circuits;

wherein the first group of clock signal lines comprises a first clock signal line, a third clock signal line and a fifth clock signal line; and

wherein the second group of clock signal lines comprises a second clock signal line, a fourth clock signal line and a sixth clock signal line.

7. The display panel according to claim 6,

wherein on one side of the display area, each of the plurality of cascaded first scan control circuits is electrically connected to the first and third clock signal lines in the first group of clock signal lines, respectively;

and each of the plurality of cascaded second scan control circuits is electrically connected to the first, third and fifth clock signal lines in the first group of clock signal lines, respectively;

wherein on another side of the display area, each of the plurality of cascaded first scan control circuits is electrically connected to the second and fourth clock signal lines in the second group of clock signal lines, respectively; and

each of the plurality of cascaded second scan control circuits is electrically connected to the second, fourth and sixth clock signal lines in the second group of clock signal lines, respectively.

8. The display panel according to claim 3, wherein one of the at least two second scan signal lines is electrically connected to one of the second scan control circuits;

and

wherein each of the first and second groups of clock signal lines comprises four clock signal lines.

9. The display panel according to claim 8,

wherein on one side of the display area, each of the plurality of cascaded first scan control circuits is electrically connected to a first clock signal line and a third clock signal line in the first group of clock signal lines, respectively;

wherein one of two adjacent second scan control circuits is electrically connected to the first and third clock signal lines in the first group of clock signal lines, and another one of said two adjacent second scan control circuits is electrically connected to a second clock signal line and a fourth clock signal line in the first group of clock signal lines;

wherein on the other side of the display area, each of the plurality of cascaded first scan control circuits is electrically connected to a second clock signal line and a fourth clock signal line in the second group of clock signal lines, respectively;

wherein one of two adjacent second scan control circuits is electrically connected to a first clock signal line and a third clock signal line in the second group of clock signal lines, and another one of said two adjacent second scan control circuits is electrically connected to the second and fourth clock signal lines in the second group of clock signal lines.

10. The display panel according to claim 8, wherein on one side of the display area, each of the plurality of cascaded first scan control circuits is electrically connected to a second clock signal line and a fourth clock signal line in the first group of clock signal lines, respectively;

wherein a second scan control circuit at a 4n+1 stage of the plurality of cascaded second scan control circuits is electrically connected to a first clock signal line and a second clock signal line in the first group of clock signal lines, respectively;

wherein a second scan control circuit at a 4n+2 stage of the plurality of cascaded second scan control circuits is electrically connected to the second clock signal line and a third clock signal line in the first group of clock signal lines, respectively;

wherein a second scan control circuit at a 4n+3 stage of the plurality of cascaded second scan control circuits is electrically connected to the third and fourth clock signal lines in the first group of clock signal lines, respectively; and

wherein a second scan control circuit at a 4n+4 stage of the plurality of cascaded second scan control circuits is electrically connected to the fourth and first clock signal lines in the first group of clock signal lines respectively;

wherein on the other side of the display area, each of the plurality of cascaded first scan control circuits is electrically connected to a first clock signal line and a third clock signal line in the second group of clock signal lines, respectively;

wherein a second scan control circuit at the 4n+1 stage of the plurality of cascaded second scan control circuits is electrically connected to the first clock signal line and a second clock signal line in the second group of clock signal lines, respectively;

a second scan control circuit at the 4n+2 stage of the plurality of cascaded second scan control circuits is electrically connected to the second and third clock signal lines in the second group of clock signal lines, respectively;

wherein the second scan control circuit at the 4n+3 stage of the plurality of cascaded second scan control circuits is electrically connected to the third clock signal line and a fourth clock signal line in the second group of clock signal lines respectively; and

wherein a second scan control circuit at the 4n+4 stage of the plurality of cascaded second scan control circuits is electrically connected to the fourth and first clock signal lines in the second group of clock signal lines respectively;

wherein n is an integer not less than 1.

11. The display panel according to claim 3, wherein one of the at least two second scan signal lines is electrically connected to one of the plurality of cascaded second scan control circuits;

wherein the first group of clock signal lines comprises a first clock signal line and a third clock signal line;

wherein the second group of clock signal lines comprises a second clock signal line and a fourth clock signal line;

wherein on one side of the display area, each of the pluralities of cascaded first and second scan control circuits is electrically connected to a first clock signal line and a third clock signal line in the first group of clock signal lines;

wherein on another side of the display area, each of the pluralities of cascaded first and second scan control circuits are all electrically connected to a second clock signal line and a fourth clock signal line in the second group of clock signal lines.

12. A method for driving a display panel,

wherein the display panel comprises a display area and a peripheral area surrounding the display area;

the display area comprises one first display area and at least one second display area;

the first display area comprises at least two first scan signal lines arranged along a first direction;

each of the at least two first scan signal lines has a first terminal and a second terminal in the first direction;

each of the at least one second display area comprises at least two second scan signal lines arranged along the first direction;

each of the at least two second scan signal lines has a third terminal close to the peripheral area in the first direction;

the first display area and the second display area are arranged along the first direction;

the peripheral area comprises a plurality of cascaded first scan control circuits close to the first and second terminals of the at least two first scan signal lines, and a plurality of cascaded second scan control circuits close to the third terminals of the at least two second scan signal lines;

each of the at least two first scan signal lines is electrically connected to one of the plurality of cascaded first scan control circuits close to the first and second terminals alternately; and

each of the at least two second scan signal lines is electrically connected to one of the plurality of cascaded second scan control circuits;

the method comprises;

receiving, by the first scan signal lines, scan signals output at the first scan control circuits close to the first terminals and second terminals of the first scan signal lines, alternately; and

receiving, by the second scan signal lines, scan signals output by the second scan control circuits close to the third terminals of the second scan signal lines.

13. The method according to claim 12, when the peripheral area has start signal lines on two opposite sides of the display area, the method further comprising:

inputting, by the start signal lines, start signals to a signal input terminal of a second scan control circuit at a first stage and to a signal input terminal of a second scan control circuit at a second stage, respectively;

transmitting, by a second scan control circuit at each stage, a scan signal output by a first signal output terminal of the second scan control circuit to a electrically connected second scan signal line;

transmitting, by a first scan control circuit at each stage, a scan signal output by a first signal output terminal of the first scan control circuit to a electrically connected first scan signal line;

transmitting, by a second scan control circuit at each odd stage, an effective pulse signal output by its second signal output terminal to a signal input terminal of a second scan control circuit at a next odd stage, except at last two stages of the second scan control circuits,

transmitting, by a second scan control circuit at each even stage, an effective pulse signal output by its second signal output terminal to a signal input terminal of a second scan control circuit at a next even stage;

transmitting, by a first scan control circuit at each stage, an effective pulse signal output by its second signal output terminal to a signal input terminal of a first scan control circuit at a next stage, except at a last stage of the first scan control circuits;

wherein on one side of the display area, transmitting, by a second scan control circuit at a last odd stage, an effective pulse signal output by its second signal output terminal to a signal input terminal of a first scan control circuit at a first stage, and wherein on the other side of the display area, transmitting, by a second scan control circuit at a last even stage, an effective pulse signal output by its second signal output terminal to a signal input terminal of a first scan control circuit at the first stage;

or, transmitting, by a second scan control circuit at a last stage, an effective pulse signal output by its second signal output terminal to a signal input terminal of a first scan control circuit at the first stage.

14. The method according to claim 13, when the peripheral area has a first group of clock signal lines and a second group of clock signal lines;

and each of the first group of clock signal lines and the second group of clock signal lines comprises four or six clock signal lines, the method further comprising;

inputting, by all the clock signal lines, clock signals successively.

15. The method according to claim 13, when the peripheral area further comprises a first group of clock signal lines and a second group of clock signal lines, the first group of clock signal lines comprises a first clock signal line, a third clock signal line and a fifth clock signal line;

and the second group of clock signal lines comprises a second clock signal line, a fourth clock signal line and a sixth clock signal line, the method further comprising;

inputting, by the first to sixth clock signal lines, clock signals successively;

wherein a pulse width of the clock signals input by the first and second groups of clock signal lines to the first scan control circuits is greater than a pulse width of the clock signals input by the first and second groups of clock signal lines to the second scan control circuits.

16. The method according to claim 13, when the peripheral area has a first group of clock signal lines and a second group of clock signal lines, the first group of clock signal lines comprises a first clock signal line, a third clock signal line and a fifth clock signal line, and the second group of clock signal lines comprises a second clock signal line, a fourth clock signal line and a sixth clock signal line, the method further comprising:

forming a time sequence of clock signals input by the first and second groups of clock signal lines to the first scan control circuits, wherein the first to sixth clock signal lines input clock signals successively;

forming a time sequence of clock signals input by the first and second groups of clock signal lines to the second scan control circuits, wherein first clock signals input by the first and the second clock signal lines input are synchronized, second clock signals input by the third and fourth clock signal lines input are synchronized, third clock signals input by the fifth and sixth clock signal lines input are synchronized; and

the first, the second and the third clock signals are successive inputs.

17. The method according to claim 14, when the peripheral area has start signal lines on two opposite sides of the display area, the method further comprising:

inputting, by the start signal lines, start signals to a signal input terminal of a second scan control circuit at a first stage;

transmitting, by a second scan control circuit at each stage, an effective pulse signal output by its signal output terminal to an electrically connected second scan signal line;

transmitting, by a first scan control circuit at each stage, an effective pulse signal output by its signal output terminal to an electrically connected first scan signal line;

transmitting, by a second scan control circuit at every other stage, except at a last stage of the second scan control circuits, an effective pulse signal output by its signal output terminal to a signal input terminal of a second scan control circuit at a next stage; and

transmitting, by a first scan control circuit at each stage, an effective pulse signal output by its signal output terminal to a signal input terminal of a first scan control circuit at a next stage, except at a last stage of the first scan control circuits;

wherein on one side of the display area, transmitting, by a second scan control circuit at the last stage, an effective pulse signal output by a signal output terminal of the second scan control circuit to a signal input terminal of a first scan control circuit at a first stage, and on the other side of the display area, transmitting, by a second scan control circuit at a second last stage, an effective pulse signal output by its signal output terminal to a signal input terminal of a first scan control circuit at the first stage;

or,

transmitting, by a second scan control circuit at the last stage, an effective pulse signal output by its second signal output terminal to a signal input terminal of a first scan control circuit at the first stage.

18. The method according to claim 12, when the peripheral area has start signal lines on two opposite sides of the display area, the method further comprising:

inputting, by the start signal lines, start signals to signal input terminals of second scan control circuits at a first stage;

transmitting, by second scan control circuits at each stage, scan signals output by their first signal output terminals to electrically connected second scan signal lines;

transmitting, by first scan control circuits at each stage, scan signals output by their first signal output terminals to electrically connected first scan signal lines;

transmitting, by second scan control circuits at each stage, effective pulse signals output by their second signal output terminals to signal input terminals of second scan control circuit at a next stage, except at a last stage of the second scan control circuits;

transmitting, by first scan control circuits at each stage, effective pulse signals output by their second signal output terminals to signal input terminals of first scan control circuits at a next stage, except at a last stage of the first scan control circuits;

wherein on one side of the display area, transmitting, by a second scan control circuit at the last stage, an effective pulse signal output by its second signal output terminal to a signal input terminal of a first scan control circuit at a first stage, and on the other side of the display area, transmitting, by a second scan control circuit at a second last stage, an effective pulse signal output by its second signal output terminal to a signal input terminal of a first scan control circuit at the first stage;

or

transmitting, by the second scan control circuits at the last stage, effective pulse signals output by their second signal output terminals to signal input terminals of first scan control circuit at the first stage

19. The method according to claim 18, when the peripheral area has a first group of clock signal lines and a second group of clock signal lines, the method further comprising:

forming a time sequence of clock signals input by the first and second groups of clock signal lines to the first scan control circuits, wherein the first to fourth clock signal lines input clock signals successively;

forming a time sequence of clock signals input by the first and second groups of clock signal lines to the second scan control circuits, wherein first clock signals input by the first and the second clock signal lines are synchronized, second clock signals input by the third and fourth clock signal lines are synchronized, and the first and the second clock signals are successive inputs.

20. The method according to claim 18, when the peripheral area has a first group of clock signal lines and a second group of clock signal lines, the first group of clock signal lines comprises a first clock signal line and a third clock signal line;

and the second group of clock signal lines comprises a second clock signal line and a fourth clock signal line, the method further comprising;

inputting, clock signals successively by the first to fourth clock signal lines;

wherein a pulse width of the clock signals input by the first and second groups of clock signal lines to the first scan control circuits is greater than a pulse width of the clock signals input by the first and second groups of clock signal lines to the second scan control circuits.