MULTI-STAGE MEMORY SENSING
First Claim
Patent Images
1. A method, comprising:
- asserting a word line signal associated with a memory cell during a read operation of the memory cell;
coupling the memory cell with a digit line associated with the memory cell based at least in part on the asserting of the word line signal;
activating a transistor to couple, during the read operation, an amplifier capacitor with the digit line;
deactivating the transistor for a portion of the read operation to isolate the amplifier capacitor from the digit line while the memory cell is coupled with the digit line;
reactivating the transistor after the portion of the read operation to recouple the amplifier capacitor with the digit line; and
determining a value stored on the memory cell after reactivating the transistor.
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Abstract
Methods and devices for reading a memory cell using multi-stage memory sensing are described. The memory cell may be coupled to a digit line after the digit line during a read operation. A transistor may be activated to couple an amplifier capacitor with the digit line during the read operation. The transistor may be deactivated for a portion of the read operation to isolate the amplifier capacitor from the digit line while the memory cell is coupled to the digit line. The transistor may be reactivated to recouple the amplifier capacitor to the digit line to help determine the value of the memory cell.
24 Citations
25 Claims
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1. A method, comprising:
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asserting a word line signal associated with a memory cell during a read operation of the memory cell; coupling the memory cell with a digit line associated with the memory cell based at least in part on the asserting of the word line signal; activating a transistor to couple, during the read operation, an amplifier capacitor with the digit line; deactivating the transistor for a portion of the read operation to isolate the amplifier capacitor from the digit line while the memory cell is coupled with the digit line; reactivating the transistor after the portion of the read operation to recouple the amplifier capacitor with the digit line; and determining a value stored on the memory cell after reactivating the transistor. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A method, comprising:
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coupling an amplifier capacitor with a second transistor by activating a first transistor, wherein the second transistor couples the first transistor with a digit line associated with a memory cell during a read operation of the memory cell; coupling the memory cell with the digit line; isolating the amplifier capacitor from the second transistor while the memory cell is coupled with the digit line by deactivating the first transistor for a portion of the read operation; recoupling the amplifier capacitor with the second transistor by reactivating the first transistor after the portion of the read operation; and determining a value stored on the memory cell after reactivating the first transistor. - View Dependent Claims (12, 13, 14, 15, 16, 17)
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18. An apparatus, comprising:
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a ferroelectric memory cell coupled with a digit line; an amplifier capacitor; a first transistor coupled with the digit line; a second transistor coupled with the first transistor and the amplifier capacitor, wherein the first transistor and the second transistor are configured to establish an electrical connection between the amplifier capacitor and the digit line during a read operation. - View Dependent Claims (19, 20)
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21. A memory device, comprising:
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a memory cell; a digit line coupled with the memory cell; an amplifier capacitor coupled with the digit line; a controller configured to; assert, during a read operation of the memory cell, a word line signal associated with the memory cell; couple the memory cell with the digit line based at least in part on the asserting of the word line signal; activate a transistor to couple, during the read operation, the amplifier capacitor with the digit line; deactivate the transistor for a portion of the read operation to isolate the amplifier capacitor from the digit line while the memory cell is coupled with the digit line; reactivate the transistor after the portion of the read operation to recouple the amplifier capacitor with the digit line; and determine a value stored on the memory cell after reactivating the transistor. - View Dependent Claims (22, 23, 24, 25)
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Specification