SEMICONDUCTOR MEMORY DEVICE CAPABLE OF SHORTENING ERASE TIME

• US 20180308557A1
• Filed: 06/29/2018
• Published: 10/25/2018
• Est. Priority Date: 12/13/2007
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Toshiba Memory Corporation (Kioxia Corporation)
• Inventors: SHIBATA, Noboru
• Granted Patent: US 10,446,247 B2
• Time in Patent Office: Days
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/14 Circuits for erasing electrically, e.g. erase voltage switching circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/3445 Circuits or methods to verify correct erasure of nonvolatile memory cells

Abstract

In a memory cell array, a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines are arranged in a matrix. A control circuit controls the potentials of said plurality of word lines and said plurality of bit lines. In an erase operation, the control circuit erases an n number of memory cells (n is a natural number equal to or larger than 2) of said plurality of memory cells at the same time using a first erase voltage, carries out a verify operation using a first verify level, finds the number of cells k (k≤n) exceeding the first verify level, determines a second erase voltage according to the number k, and carries out an erase operation again using the second erase voltage.

Claims

1. (canceled)

2. :

A semiconductor memory device comprising;

a memory cell array including memory cells, the memory cells arranged in the memory cell array in a matrix form, and the memory cells connected to word lines and bit lines;

a control circuit configured to control voltages of the word lines and the bit lines,

wherein, in a read operation for a first memory cell among the memory cells, the control circuit applies a first voltage to a first word line among the word lines, the first word line connected to the first memory cell, and

the control circuit applies a second voltage lower than the first voltage to the first word line to read a data of the first memory cell.

3. :

the device according to claim 2, wherein

a time of an application of the first voltage is shorter than a time of an application of the second voltage.

4. :

The device according to claim 2, wherein

the memory cells includes a second memory cell, the second memory cell is connected to the first memory cell in series and a second word line among the word lines, and

the control circuit applies a third voltage to the second word line during an application of the first voltage to the first word line.

5. :

The device according to claim 4, wherein

the third voltage is higher than the first voltage.

6. :

The device according to claim 4, wherein

the control circuit applies the third voltage to the second word line during an application of the second voltage to the first word line.