Forming a Protective Layer to Prevent Formation of Leakage Paths

• US 20180308760A1
• Filed: 06/25/2018
• Published: 10/25/2018
• Est. Priority Date: 11/30/2016
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Hsu, Leo, Lin, Louis
• Granted Patent: US 10,446,449 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/02115 the material being carbon, e.g. alpha-C, diamond or hydrogen doped carbon
• CPC Class Codes: H01L 21/0217 the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz H01L21/02126 and H01L21/0214 take precedence
• CPC Class Codes: H01L 21/02274 in the presence of a plasma [PECVD]
• CPC Class Codes: H01L 21/28008 Making conductor-insulator-semiconductor electrodes
• CPC Class Codes: H01L 21/31058 of organic layers
• CPC Class Codes: H01L 21/31111 by chemical means
• CPC Class Codes: H01L 21/31144 using masks
• CPC Class Codes: H01L 21/76802 by forming openings in dielectrics
• CPC Class Codes: H01L 21/76816 Aspects relating to the layout of the pattern or to the size of vias or trenches layout of the interconnections per se H01L23/528; CAD of ICs G06F30/00
• CPC Class Codes: H01L 21/76831 in via holes or trenches, e.g. non-conductive sidewall liners
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 21/823475 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 2221/1063 Sacrificial or temporary thin dielectric films in openings in a dielectric

Abstract

A gate structure is formed over a substrate. The gate structure includes a gate electrode and a hard mask located over the gate electrode. The hard mask comprises a first dielectric material. A first interlayer dielectric (ILD) is formed over the gate structure. The first ILD comprises a second dielectric material different from the first dielectric material. A first via is formed in the first ILD. Sidewalls of the first via are surrounded by spacers that comprise the first dielectric material. A second ILD is formed over the first ILD. A via hole is formed in the second ILD. The via hole exposes the first via. A protective layer is formed in the via hole. A bottom segment of the protective layer is removed. Thereafter, an etching process is performed. A remaining segment of the protective layer prevents an etching of the spacers during the etching process.

Claims

1. A method of fabricating a semiconductor device, comprising:

forming a recess in a dielectric layer, the recess exposing a first via that vertically extends through the dielectric layer, wherein spacers are formed on sidewalls of the first via;

forming a first layer in the recess, the first layer and the spacers having different material compositions; and

after the first layer is formed, etching a second layer that has a same material composition as the spacers, wherein the first layer prevents the spacers from being etched.

2. The method of claim 1, wherein the recess is formed to be wider than a top surface of the first via.

3. The method of claim 1, wherein the recess is formed in a manner such that top surfaces of the spacers are partially exposed by the recess.

4. The method of claim 3, wherein the top surfaces of the spacers that are partially exposed by the recess are covered up by the first layer.

5. The method of claim 1, wherein the forming of the first layer comprises forming a polymer as the first layer.

6. The method of claim 5, wherein the forming the polymer comprises forming a methane, a methylene, or a methylene bridge as the polymer.

7. The method of claim 1, wherein the forming the first layer comprises performing a deposition process using a CH₄ precursor.

8. The method of claim 1, wherein the forming the first layer comprises forming the first layer having a thickness in a range between 4 nanometers and 6 nanometers.

9. The method of claim 1, further comprising:

before the etching of the second layer, etching the first layer to remove a bottom segment of the first layer.

10. The method of claim 9, further comprising:

after the etching of the second layer, completely removing the first layer.

11. The method of claim 1, wherein:

the forming of the recess comprises forming a first recess and a second recess, the first recess exposing the first via, the second recess being aligned with a gate structure; and

the forming of the first layer comprises forming the first layer in both the first recess and the second recess.

12. The method of claim 11, wherein the etching of the second layer comprises extending the second recess through the second layer to expose a portion of the gate structure.

13. The method of claim 11, further comprising:

forming a second via in the first recess and a third via in the second recess.

14. A method of fabricating a semiconductor device, comprising:

forming a first trench and a second trench, wherein the first trench is aligned with a gate structure and vertically extends through a first dielectric layer and through a second dielectric layer disposed over the first dielectric layer, wherein the second trench is aligned with a source/drain and extends through the second dielectric layer but not through the first dielectric layer, and wherein the second trench exposes a conductive via that is surrounded by spacers;

forming a protective layer on surfaces of the first trench and the second trench, wherein the protective layer and the spacers have different material compositions;

performing a first etching process to remove a bottom segment of the protective layer in the first trench and the second trench; and

performing a second etching process to extend the first trench further downward, thereby exposing a portion of the gate structure, wherein the protective layer in the second trench protects the spacers during the second etching process.

15. The method of claim 14, wherein:

the second etching process comprises extending the first trench vertically downward through an etching-stop layer and a mask layer that are disposed over the gate structure; and

the etching-stop layer or the mask layer have a same material composition as the spacers.

16. The method of claim 14, further comprising:

removing the protective layer after the second etching process has been performed; and

after the removing of the protective layer, forming additional vias that fill the first trench and the second trench.

17. A semiconductor device, comprising:

a source/drain formed in a substrate;

a first via disposed over and electrically coupled to the source/drain;

a second via disposed over and electrically coupled to the first via;

spacers disposed on sidewalls of the second via; and

a third via disposed over and electrically coupled to the second via, wherein a bottom surface of the third via is in physical contact with a portion of a top surface of the spacers.

18. The semiconductor device of claim 17, wherein the bottom surface of the third via has a greater lateral dimension than a top surface of the second via.

19. The semiconductor device of claim 17, further comprising:

a gate structure disposed over the substrate, the gate structure including a gate electrode; and

a fourth via disposed over and electrically coupled to the gate electrode of the gate structure.

20. The semiconductor device of claim 19, further comprising:

a mask layer disposed over the gate electrode; and

an etching-stop layer disposed over the mask layer;

wherein;

the fourth via vertically extends through the mask layer and the etching-stop layer; and

at least one of the mask layer and the etching-stop layer has a same material composition as the spacers.