Memory Cells and Memory Arrays

• US 20180308853A1
• Filed: 10/27/2017
• Published: 10/25/2018
• Est. Priority Date: 04/21/2017
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Bell, Debra M., Derner, Scott J.
• Granted Patent: US 10,177,159 B2
• Time in Patent Office: Days
• CPC Class Codes: G11C 11/412 using field-effect transistors only
• CPC Class Codes: G11C 11/419 Read-write [R-W] circuits
• CPC Class Codes: H01L 21/76202 using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO H01L21/76235 takes precedence; together with vertical isolation, e.g. LOCOS in a SOI substrate, H01L21/76264
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H10B 10/12 comprising a MOSFET load element
• CPC Class Codes: H10B 10/125 the MOSFET being a thin film transistor [TFT]
• CPC Class Codes: H10B 10/15 comprising a resistor load element

Abstract

Some embodiments include memory cells having four transistors supported by a base, and vertically offset from the base. The four transistors are incorporated into first and second inverters having first and second inverter outputs, respectively. A first access transistor gatedly couples the first inverter output to a first comparative bitline, and second access transistor gatedly couples the second inverter output to a second comparative bitline. The first and second access transistors have first and second gates coupled to one another through a wordline. The four transistors are along a first side of the wordline, and are vertically displaced from the wordline. The first and second comparative bitlines are laterally adjacent to one another along a second side of the wordline, and are vertically displaced from the wordline. Some embodiments include memory arrays.

Claims

1. A memory cell, comprising:

two pulldown devices and two pullup devices supported by a base and vertically offset from the base;

the two pulldown devices being first and second pulldown devices, and the two pullup devices being first and second pullup devices;

the first pullup device and first pulldown device being together comprised by a first inverter;

the second pullup device and second pulldown device being together comprised by a second inverter;

the first and second inverters having first and second inverter outputs, respectively;

the first and second pullup devices being vertically stacked one atop another;

the first and second pulldown devices being vertically stacked one atop another;

a first access transistor gatedly coupling the first inverter output to a first comparative bitline;

the first access transistor having a first access transistor gate;

a second access transistor gatedly coupling the second inverter output to a second comparative bitline;

the second access transistor having a second access transistor gate;

the first and second access transistor gates being coupled to one another through a wordline;

the wordline having a first side and an opposing second side, with the second side being vertically displaced relative to the first side;

the first and second inverters being along the first side of the wordline, and being vertically displaced from the wordline; and

the first and second comparative bitlines being laterally adjacent to one another along the second side of the wordline, and being vertically displaced from the wordline.

2. The memory cell of claim 1, wherein the pulldown devices are n-channel transistors.

3. The memory cell of claim 2, wherein at least one of the pullup devices is a p-channel transistor.

4. The memory cell of claim 2, wherein at least one of the pullup devices is a resistor.

5. A memory cell, comprising:

four transistors supported by a base and vertically offset from the base;

the four transistors including first and second p-channel transistors, and first and second n-channel transistors;

the first p-channel transistor and first n-channel transistor being together comprised by a first inverter;

the second p-channel transistor and second n-channel transistor being together comprised by a second inverter;

the first and second inverters having first and second inverter outputs, respectively;

the first and second p-channel transistors being vertically stacked one atop another;

the first and second n-channel transistors being vertically stacked one atop another;

a first access transistor gatedly coupling the first inverter output to a first comparative bitline;

the first access transistor having a first access transistor gate;

a second access transistor gatedly coupling the second inverter output to a second comparative bitline;

the second access transistor having a second access transistor gate;

the first and second access transistor gates being coupled to one another through a wordline;

the wordline having a first side and an opposing second side, with the second side being vertically displaced relative to the first side;

the four transistors being along the first side of the wordline, and being vertically displaced from the wordline; and

the first and second comparative bitlines being laterally adjacent to one another along the second side of the wordline, and being vertically displaced from the wordline.

6. The memory cell of claim 5, wherein:

the vertically stacked first and second n-channel transistors are comprised by a first stack;

the vertically-stacked first and second p-channel transistors are comprised by a second stack; and

the second stack is laterally displaced from the first stack and horizontally aligned with the first stack.

7. A memory array comprising the memory cell of claim 6 as one memory cell within a plurality of memory cells;

wherein

an axis through the first and second comparative bitlines defines a mirror plane; and

another memory cell is on an opposing side of the mirror plane from said one memory cell and is substantially a mirror image of said one memory cell across the mirror plane;

said other memory cell sharing the first and second comparative bitlines with said one memory cell.

8. The memory cell of claim 6, wherein:

the first p-channel transistor has a first pullup gate surrounding a first channel region;

the second p-channel transistor has a second pullup gate surrounding a second channel region;

the first n-channel transistor has a first pulldown gate surrounding a third channel region;

the second n-channel transistor has a second pulldown gate surrounding a fourth channel region;

the first, second, third and fourth channel regions are within first, second third and fourth vertically-extending pillars, respectively;

the first vertically-extending pillar is over the second vertically-extending pillar; and

the third vertically-extending pillar is over the fourth vertically-extending pillar.

9. The memory cell of claim 8, wherein:

the first and second vertically-extending pillars are aligned within one another along a first vertical axis; and

the third and fourth vertically-extending pillars are aligned within one another along a second vertical axis which is laterally displaced relative to the first vertical axis.

10. The memory cell of claim 5, wherein the all four of the transistors are vertically stacked one atop another.

11. The memory cell of claim 10, wherein both of the p-channel transistors are over both of the n-channel transistors.

12. The memory cell of claim 10, wherein:

the first p-channel transistor has a first pullup gate surrounding a first channel region;

the second p-channel transistor has a second pullup gate surrounding a second channel region;

the first n-channel transistor has a first pulldown gate surrounding a third channel region;

the second n-channel transistor has a second pulldown gate surrounding a fourth channel region;

the first, second, third and fourth channel regions are within first, second third and fourth vertically-extending pillars, respectively; and

the second vertically-extending pillar is over the first vertically-extending pillar which is over the third vertically-extending pillar which is over the fourth vertically-extending pillar.

13. The memory cell of claim 12, wherein the first, second, third and fourth vertically-extending pillars are aligned within one another along a vertical axis.

14. The memory cell of claim 13, wherein

a first circuit supply line is vertically between the first and second p-channel transistors and is coupled with source regions of the first and second p-channel transistors;

a second circuit supply line is vertically between the first and second n-channel transistors and is coupled with source regions of the first and second n-channel transistors;

the first circuit supply line is coupled with a first reference voltage and the second circuit supply line is coupled with a second reference voltage; and

the first reference voltage is higher than the second reference voltage.

15. A memory array comprising the memory cell of claim 10 as one memory cell within a plurality of memory cells;

wherein

an axis through the first and second comparative bitlines defines a mirror plane; and

another memory cell is on an opposing side of the mirror plane from said one memory cell and is substantially a mirror image of said one memory cell across the mirror plane;

said other memory cell sharing the first and second comparative bitlines with said one memory cell.

16. An apparatus comprising:

a memory array having rows and columns;

wordlines along the rows;

comparative bitlines along the columns;

the comparative bitlines being in pairs along each column;

each pair of the comparative bitlines including a first comparative bitline and a second comparative bitline;

a plurality of memory cells;

each memory cell within the plurality of memory cells being uniquely addressed with one of the wordlines and one pair of the comparative bitlines;

each memory cell within the plurality of memory cells comprising two p-channel transistors and two n-channel transistors, with the p-channel and n-channel transistors being arranged within a first inverter and a second inverter;

the first and second inverters having first and second inverter outputs, respectively;

each memory cell within the plurality of memory cells comprising a first access transistor gatedly coupling the first inverter output with a first comparative bitline of a pair of comparative bitlines uniquely addressing the memory cell, and a second access transistor gatedly coupling the second inverter output with a second comparative bitline of the pair of comparative bitlines uniquely addressing the memory cell;

the first and second access transistors having gates coupled with a wordline uniquely addressing the memory cell;

one of the memory cells within the plurality of memory cells being a first memory cell and being uniquely addressed by a first wordline and a first pair of the comparative bitlines;

the first and second comparative bitlines of said first pair being laterally adjacent to one another and on an opposing side of the first wordline from the p-channel transistors and the n-channel transistors of the first memory cell;

one of the memory cells within the plurality of memory cells being a second memory cell vertically stacked relative to the first memory cell and sharing the first pair of the comparative bitlines; and

the second memory cell being substantially a mirror image of the first memory cell across a plane extending through the first pair of the comparative bitlines.

17. The apparatus of claim 16 comprising a second wordline utilized with the first pair of the comparative bitlines to uniquely address the second memory cell;

the first and second memory cells being a first set of stacked memory cells;

one of the memory cells within the plurality of memory cells being a third memory cell, and another memory cell within the plurality of memory cells being a fourth memory cell; and

the apparatus comprising;

the third and fourth memory cells being laterally adjacent the first and second memory cells;

the third and fourth memory cells being vertically stacked one atop another and being a second set of stacked memory cells laterally displaced from the first set of stacked memory cells along the first and second wordlines; and

the third and fourth memory cells being substantially mirror images of one another across a plane extending through a second pair of the comparative bitlines.

18. An apparatus comprising:

a semiconductor base;

a memory array supported by the semiconductor base;

the memory array including a memory cell;

the memory cell comprising four transistors vertically stacked one atop another;

the four transistors including first and second p-channel transistors, and first and second n-channel transistors;

the first p-channel transistor and first n-channel transistor being together comprised by a first inverter;

the second p-channel transistor and second n-channel transistor being together comprised by a second inverter;

the first and second inverters having first and second inverter outputs, respectively;

the first and second p-channel transistors having first and second pullup gates, respectively;

the first and second n-channel transistors having first and second pulldown gates, respectively;

the first pullup gate and the second pulldown gate being coupled to a first vertically-extending interconnect structure comprising the first inverter output;

the second pullup gate and the first pulldown gate being coupled to a second vertically-extending interconnect structure comprising the second inverter output;

the first and second vertically-extending interconnect structures being laterally offset from one another and being spaced from one another by an intervening region comprising said four transistors;

a first access transistor gatedly coupling the first inverter output to a first comparative bitline;

the first access transistor having a first access transistor gate;

a second access transistor gatedly coupling the second inverter output to a second comparative bitline;

the second access transistor having a second access transistor gate;

the first and second access transistor gates being coupled to one another through a wordline;

the wordline being over said four transistors; and

the first and second comparative bitlines being laterally adjacent to one another and on an opposing side of said wordline from said four transistors.

19. The apparatus of claim 18, wherein the first and second pullup gates comprise n-type doped semiconductor material, and wherein the first and second pulldown gates comprise p-doped semiconductor material.

20. The apparatus of claim 19, wherein the first and second vertically-extending interconnect structures comprise one or more of metal, conductively-doped semiconductor, metal nitride, metal carbide and metal silicide.

21. The apparatus of claim 18, wherein said intervening region is a first-type of intervening region and includes channel pillars comprised by each of said four transistors;

wherein the memory cell is one of a plurality of memory cells within the memory array, with the memory cells of said plurality being arranged in rows and columns of the memory array;

the wordline being one of a plurality of wordlines and extending along one of the rows of the memory array, and the first and second comparative bitlines being paired comparative bitlines and extending along one of the columns of the memory array;

the paired comparative bitlines extending to a pair of conductive contacts proximate said one of the columns of the memory array;

one of the conductive contacts being a first conductive contact and being configured identically to the first vertically-extending interconnect structure, and the other of the conductive contacts being a second conductive contact and being configured identically to the second vertically-extending interconnect structure;

the first and second conductive contacts coupling the first and second comparative bitlines, respectively, of said one of the columns of the memory array with circuitry external of the memory array; and

the first and second conductive contacts being laterally spaced from one another by a second type of intervening region identical to the first type of intervening region but lacking the channel pillars.

22. The apparatus of claim 18, wherein said intervening region is a first-type of intervening region and includes channel pillars comprised by each of said four transistors;

wherein the memory cell is one of a plurality of memory cells within the memory array, with the memory cells of said plurality being arranged in rows and columns of the memory array;

the wordline being one of a plurality of wordlines and extending along one of the rows of the memory array, and the first and second comparative bitlines being paired comparative bitlines and extending along one of the columns of the memory array;

the wordline extending to a pair of conductive contacts;

one of the conductive contacts being a first conductive contact and being configured identically to the first vertically-extending interconnect structure, and the other of the conductive contacts being a second conductive contact and being configured identically to the second vertically-extending interconnect structure;

at least one of the first and second conductive contacts coupling the wordline with wordline driver circuitry external of the memory array; and

the first and second conductive contacts being laterally spaced from one another by a second type of intervening region identical to the first type of intervening region but lacking the channel pillars.

23. The apparatus of claim 18, wherein the memory cell is a first memory cell and is one of a plurality of memory cells within the memory array, with the memory cells of said plurality being arranged in rows and columns of the memory array;

the wordline is a first wordline and is one of a plurality of wordlines extending along the rows of the memory array, and the first and second comparative bitlines being paired comparative bitlines and extend along one of the columns of the memory array;

a second memory cell of the plurality of memory cells being stacked over the first memory cell and sharing the paired comparative bitlines with the first memory cell; and

the first and second memory cells being substantially mirror images of one another across a plane extending through the paired comparative bitlines.

24. The apparatus of claim 23 wherein the plurality of wordlines includes a second wordline;

the first wordline being between the first memory cell and the paired comparative bitlines;

the second wordline being between the second memory cell and the paired comparative bitlines;

the stacked first and second memory cells being a first set of stacked memory cells, and the paired comparative bitlines being a first set of paired comparative bitlines;

a second set of stacked memory cells being laterally displaced from the first set of stacked memory cells along the first and second wordlines;

the second set of stacked memory cells including a third memory cell and a fourth memory cell of the plurality of memory cells; and

the third and fourth memory cells being substantially mirror images of one another across a plane extending through a second set of paired comparative bitlines.

25. The apparatus of claim 24, wherein the second set of paired comparative bitlines is horizontally aligned with the first set of paired comparative bitlines.