NON-VOLATILE MEMORY DEVICES WITH VERTICALLY INTEGRATED CAPACITOR ELECTRODES

• US 20180308857A1
• Filed: 06/05/2018
• Published: 10/25/2018
• Est. Priority Date: 05/02/2014
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: KIM, HYUN-SUK, LEE, JOON-HEE, RHO, KEE-JEONG
• Granted Patent: US 10,236,298 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 28/60 Electrodes
• CPC Class Codes: H01L 28/91 made by depositing layers, e.g. by depositing alternating conductive and insulating layers
• CPC Class Codes: H10B 41/10 characterised by the top-view layout
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 41/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 43/10 characterised by the top-view layout
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/30 characterised by the memory core region
• CPC Class Codes: H10B 43/35 with cell select transistors, e.g. NAND
• CPC Class Codes: H10B 43/40 characterised by the peripheral circuit region

Abstract

Provided is a vertical non-volatile memory device in which a capacitor constituting a peripheral circuit region is formed as a vertical type so that an area occupied by the capacitor in the entire device can be reduced as compared with a planar capacitor. Thus, a non-volatile memory device may be highly integrated and have a high capacity. The device includes a substrate having a cell region and a peripheral circuit region, a memory cell string including a plurality of vertical memory cells formed in the cell region and channel holes formed to penetrate the vertical memory cells in a first direction vertical to the substrate, an insulating layer formed in the peripheral circuit region on the substrates at substantially the same level as an upper surface of the memory cell string, and a plurality of capacitor electrodes formed on the peripheral circuit region to penetrate at least a portion of the insulating layer in the first direction, the plurality of capacitor electrodes extending parallel to the channel holes. The plurality of capacitor electrodes are spaced apart from one another in a second direction parallel to the substrate, and the insulating layer is interposed between a pair of adjacent capacitor electrodes from among the plurality of capacitor electrodes.

Claims

1. A nonvolatile memory device, comprising:

a substrate having a cell region and a peripheral circuit region;

a memory cell string including a plurality of vertical memory cells formed in the cell region and a plurality of channel holes formed to penetrate the vertical memory cells in a first direction vertical to an upper surface of the substrate;

an insulating layer formed in the peripheral circuit region on the substrate at substantially same level as an upper surface of the memory cell string; and

a plurality of capacitor electrodes formed on the peripheral circuit region to penetrate at least a portion of the insulating layer in the first direction, wherein the plurality of capacitor electrodes are spaced apart from each other in a direction parallel to the upper surface of the substrate and are spaced apart from the substrate so that lowermost surfaces of the plurality of capacitor electrodes are at a higher level than the upper surface of the substrate.

2. A nonvolatile memory device, comprising:

a substrate having a cell region and a peripheral circuit region;

a memory cell string including a plurality of vertical memory cells formed in the cell region and a plurality of channel holes formed to penetrate the vertical memory cells in a first direction vertical to an upper surface of the substrate;

an insulating layer formed in the peripheral circuit region on the substrate at substantially same level as an upper surface of the memory cell string; and

a plurality of capacitor electrodes formed on the peripheral circuit region to penetrate at least a portion of the insulating layer in the first direction, wherein the plurality of capacitor electrodes are spaced apart from each other in a direction parallel to the upper surface of the substrate, and are spaced apart from the substrate and have a pitch that is substantially the same as a pitch of the plurality of channel holes.

3. The device of claim 2, further comprising an insulating film between the substrate and the lowermost surfaces of the plurality of capacitor electrodes.