SiC Semiconductor Device with Offset in Trench Bottom

• US 20180308938A1
• Filed: 04/23/2018
• Published: 10/25/2018
• Est. Priority Date: 04/24/2017
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Siemieniec, Ralf, Aichinger, Thomas, Esteve, Romain, Kueck, Daniel
• Granted Patent: US 10,553,685 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/417 carrying the current to be rectified, amplified or switched
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/66068 the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A semiconductor device includes a trench extending from a first surface into a SiC semiconductor body. The trench has a first sidewall, a second sidewall opposite to the first sidewall, and a trench bottom. A gate electrode is arranged in the trench and is electrically insulated from the SiC semiconductor body by a trench dielectric. A body region of a first conductivity type adjoins the first sidewall. A shielding structure of the first conductivity type adjoins at least a portion of the second sidewall and the trench bottom. A first section of the trench bottom and a second section of the trench bottom are offset to one another by a vertical offset along a vertical direction extending from the first surface to a second surface of the SiC semiconductor body opposite to the first surface.

Claims

1. A semiconductor device, comprising:

a trench extending from a first surface into a SiC semiconductor body, the trench having a first sidewall, a second sidewall opposite to the first sidewall, and a trench bottom;

a gate electrode arranged in the trench and electrically insulated from the SiC semiconductor body by a gate dielectric;

a body region of a first conductivity type adjoining the first sidewall; and

a shielding structure of the first conductivity type adjoining at least a portion of the second sidewall and the trench bottom,

wherein along a vertical direction extending from the first surface to a second surface of the SiC semiconductor body opposite to the first surface, a first section of the trench bottom and a second section of the trench bottom are offset to one another by a vertical offset.

2. The semiconductor device of claim 1, wherein the shielding structure includes a shielding region of the first conductivity type and a connection region of the first conductivity type, the connection region being arranged between the shielding region and the first surface, wherein a doping concentration profile of the shielding region has a peak along the vertical direction that is located deeper in the SiC semiconductor body than the trench bottom.

3. The semiconductor device of claim 2, wherein a vertical distance between the first section of the trench bottom and the peak of the shielding region ranges from 200 nm to 800 nm.

4. The semiconductor device of claim 1, wherein the second section of the trench bottom is arranged deeper in the SiC semiconductor body than the first section of the trench bottom.

5. The semiconductor device of claim 1, wherein the vertical offset ranges from 10 nm to 100 nm.

6. The semiconductor device of claim 1, wherein a second section of a bottom of the gate electrode is arranged deeper in the SiC semiconductor body along the vertical direction than a first section of the bottom of the gate electrode.

7. The semiconductor device of claim 1, further comprising:

a source region of a second conductivity type between the body region and the first surface,

wherein a first portion of the source region is arranged between the first sidewall of the trench and a second portion of the source region,

wherein a bottom of the second portion of the source region is arranged deeper in the SiC semiconductor body along the vertical direction than a bottom of the first portion.

8. The semiconductor device of claim 7, wherein a vertical distance between the bottom of the first portion of the source region and the bottom of the second portion of the source region corresponds to a vertical distance between the first section of the trench bottom and the second section of the trench bottom.

9. The semiconductor body of claim 1, wherein the shielding structure adjoins the second sidewall at the first surface.

10. The semiconductor device of claim 1, further comprising a region of a second conductivity type adjoining the second sidewall and the first surface.

11. The semiconductor device of claim 1, wherein a thickness of a first part of the gate dielectric adjoining the trench bottom is greater than a thickness of a second part of the gate dielectric adjoining the first and second sidewalls.

12. The semiconductor device of claim 1, further comprising:

a current spread zone of a second conductivity type; and

a drift zone of the second conductivity type,

wherein the current spread zone is arranged between the body region and the drift zone,

wherein the current spread zone adjoins the body region and the shielding structure,

wherein an average net doping concentration of the current spread zone is greater than an average net doping concentration of the drift zone.

13. The semiconductor device of claim 1, wherein the SiC semiconductor body is a 4H-SiC semiconductor body, and wherein a sidewall plane of the first sidewall is (11-20).

14. The semiconductor device of claim 1, further comprising:

a plurality of transistor cells electrically connected in parallel,

wherein each one of the plurality of transistor cells comprises the trench, the gate dielectric, the gate electrode, and the shielding structure.

15. A method of manufacturing a semiconductor device, the method comprising:

forming a first trench extending from a first surface into a SiC semiconductor body;

forming a shielding structure of a first conductivity type in the SiC semiconductor body by introducing dopants of a first conductivity type through a bottom of the first trench into the SiC semiconductor body; and

forming a second trench extending from the first surface into the SiC semiconductor body,

wherein the second trench extends deeper into the SiC semiconductor body than the first trench,

wherein the first trench and the second trench laterally merge one another so as to set a second section of a trench bottom of the second trench deeper in the SiC semiconductor body than a first section of the trench bottom of the second trench.

16. The method of claim 15, wherein forming the first trench comprises etching the SiC semiconductor body covered by a patterned hard mask.

17. The method of claim 15, wherein a depth of the first trench ranges from 10 nm to 100 nm.

18. The method of claim 15, wherein forming the shielding structure comprises introducing dopants of the first conductivity type into the SiC semiconductor body by at least one ion implantation with an ion implantation energy ranging from 1 MeV to 6 MeV.

19. The method of claim 15, wherein forming the shielding structure comprises:

forming a shielding region of the first conductivity type; and

forming a connection region of the first conductivity type, the connection region being arranged between the shielding region and the first surface,

wherein a doping concentration profile of the shielding region along a vertical direction perpendicular to the first surface is set to have a peak,

wherein the peak is set deeper in the SiC semiconductor body than the trench bottom of the second trench.

20. The method of claim 19, wherein a vertical distance between the first section of the trench bottom and the peak of the shielding region ranges from 200 nm to 800 nm.

21. The method of claim 15, further comprising:

forming a source region before forming the second trench;

lining first and second sidewalls and a bottom of the second trench with a gate dielectric; and

forming a gate electrode in the second trench.