SWITCH MODE POWER CONVERTER CURRENT SENSING APPARATUS AND METHOD

• US 20180313873A1
• Filed: 07/03/2018
• Published: 11/01/2018
• Est. Priority Date: 08/15/2012
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Hu, Yongxuan, Hoque, Mohammad Rashedul
• Granted Patent: US 11,467,189 B2
• Time in Patent Office: Days
• CPC Class Codes: G01R 19/00 Arrangements for measuring currents or voltages or for indicating presence or sign thereof G01R5/00 takes precedence; for measuring bioelectric currents or voltages A61B5/24
• CPC Class Codes: G01R 19/0092 measuring current only all subgroups of G01R19/00 take precedence
• CPC Class Codes: G05F 1/10 Regulating voltage or current G05F1/02 takes precedence; for electric railways B60M3/02
• CPC Class Codes: H02M 3/156 with automatic control of output voltage or current, e.g. switching regulators
• CPC Class Codes: H02M 3/158 including plural semiconductor devices as final control devices for a single load
• CPC Class Codes: H02M 3/1582 Buck-boost converters H02M3/1584 takes precedence

Abstract

Methods and apparatus are presented for sensing current flowing in a power transistor of a switch mode converter, in which a voltage is sensed across a first field effect transistor connected in a series circuit branch in parallel with the power transistor, and the sensed voltage is used to generate output signal to indicate the current flowing in the power transistor.

Claims

1. An integrated circuit, comprising:

a first transistor having a first drain, a first gate, and a first source;

a switch node coupled to the first source;

an auxiliary circuit coupled in parallel with the first transistor, the auxiliary circuit including a second transistor having a second drain, a second gate coupled to an internal node configured to receive a constant voltage, and a second source coupled to the first drain of the first transistor; and

a sense circuit including a third transistor having a third drain, a third gate coupled to the internal node configured to receive the constant voltage, and a third source.

2. The integrated circuit of claim 1, wherein the auxiliary circuit includes a fourth transistor having a fourth drain coupled to the second drain of the second transistor, a fourth gate coupled to the first gate of the first transistor, and a fourth source coupled to the first source of the first transistor.

3. The integrated circuit of claim 1, wherein the auxiliary circuit includes a capacitor having a first terminal coupled to the second drain of the second transistor, and a second terminal coupled to a ground node.

4. The integrated circuit of claim 1, further comprising:

a voltage input terminal, wherein the first drain of the first transistor is coupled to the voltage input terminal, and the third source of the third transistor is coupled to the first drain of the first transistor.

5. The integrated circuit of claim 1, further comprising:

a converter controller configured to generate a pulse width modulation (PWM) signal based on a sense voltage received from the sense circuit; and

a buck driver configured to generate a driver signal based on the PWM signal received from the converter controller, and the buck driver configured to deliver the driver signal to the first gate of the first transistor.

6. The integrated circuit of claim 1, further comprising:

a voltage output terminal, wherein the first drain of the first transistor is coupled to the voltage output terminal, and the third drain of the third transistor is coupled to the second drain of the second transistor.

7. The integrated circuit of claim 1, further comprising:

a converter controller configured to generate a pulse width modulation (PWM) signal based on a sense voltage received from the sense circuit; and

a boost driver configured to generate a driver signal based on the PWM signal received from the converter controller, and the boost driver configured to deliver the driver signal to the first gate of the first transistor.

8. The integrated circuit of claim 1, further comprising:

a high side switch including the first transistor;

a low side switch including a fourth transistor having a fourth drain coupled to the switch node, a fourth gate, and a fourth source coupled to a ground node; and

a driver circuit configured to generate a first driver signal for the high side switch, and a second driver signal for the low side switch.

9. The integrated circuit of claim 1, further comprising:

a diode including an anode coupled to a ground node, and a cathode coupled to the switch node.

10. An integrated circuit, comprising:

a first transistor having a first drain, a first gate, and a first source;

a switch node coupled to the first source;

an auxiliary circuit coupled in parallel with the first transistor, the auxiliary circuit including a second transistor having a second drain, a second gate coupled to an internal node configured to receive a constant voltage, and a second source coupled to the first drain of the first transistor; and

a sense circuit coupled between the second source and the second drain of the second transistor, the sense circuit configured to generate a sense voltage representative of an auxiliary current to be conducted by the second transistor.

11. The integrated circuit of claim 10, wherein the sense circuit includes:

a third transistor having a third drain, a third gate coupled to the internal node configured to receive the constant voltage, and a third source coupled to the first drain of the first transistor.

12. The integrated circuit of claim 10, further comprising:

a converter controller configured to generate a pulse width modulation (PWM) signal based on the sense voltage received from the sense circuit; and

a buck driver configured to generate a driver signal based on the PWM signal received from the converter controller, and the buck driver configured to deliver the driver signal to the first gate of the first transistor.

13. The integrated circuit of claim 10, wherein the sense circuit includes:

a third transistor having a third drain coupled to the second drain of the second transistor, a third gate coupled to the internal node configured to receive the constant voltage, and a third source.

14. The integrated circuit of claim 10, further comprising:

a converter controller configured to generate a pulse width modulation (PWM) signal based on the sense voltage received from the sense circuit; and

a boost driver configured to generate a driver signal based on the PWM signal received from the converter controller, and the boost driver configured to deliver the driver signal to the first gate of the first transistor.

15. The integrated circuit of claim 10, wherein the auxiliary circuit includes a third transistor having a third drain coupled to the second drain of the second transistor, a third gate coupled to the first gate of the first transistor, and a third source coupled to the first source of the first transistor.

16. A USB Power Delivery (PD) device, comprising:

an input terminal, a switch node, and an output terminal

a first transistor having a first drain coupled to the input terminal, a first gate, and a first source coupled to the switch node;

an auxiliary circuit coupled in parallel with the first transistor, the auxiliary circuit including a second transistor having a second drain, a second gate, and a second source coupled to the first drain; and

a sense circuit including a third transistor having a third drain, a third gate coupled to the second gate, and a third source coupled to the first drain.

17. The USB PD device of claim 16, wherein the auxiliary circuit includes a fourth transistor having a fourth drain coupled to the second drain of the second transistor, a fourth gate coupled to the first gate of the first transistor, and a fourth source coupled to the first source of the first transistor.

18. The USB PD device of claim 16, wherein the auxiliary circuit includes a capacitor having a first terminal coupled to the second drain of the second transistor, and a second terminal coupled to a ground node.

19. The USB PD device of claim 16, further comprising:

a high side switch including the first transistor;

a low side switch including a fourth transistor having a fourth drain coupled to the switch node, a fourth gate, and a fourth source coupled to a ground node; and

a driver circuit configured to generate a first driver signal for the high side switch, and a second driver signal for the low side switch.

20. The USB PD device of claim 16, further comprising:

a converter controller configured to generate a pulse width modulation (PWM) signal based on a sense voltage received from the sense circuit; and

a buck driver configured to generate a driver signal based on the PWM signal received from the converter controller, and the buck driver configured to deliver the driver signal to the first gate of the first transistor.