DESIGN LAYOUT PATTERN PROXIMITY CORRECTION THROUGH EDGE PLACEMENT ERROR PREDICTION

• US 20180314148A1
• Filed: 05/01/2017
• Published: 11/01/2018
• Est. Priority Date: 05/01/2017
• Status: Active Grant

• Current Assignee: Lam Research Corporation
• Original Assignee: Lam Research Corporation
• Inventors: Tetiker, Mehmet Derya, Sriraman, Saravanapriyan, Bailey, III, Andrew D., Wise, Richard
• Granted Patent: US 10,534,257 B2
• Time in Patent Office: Days
• CPC Class Codes: G03F 1/36 Masks having proximity correction features; Preparation thereof, e.g. optical proximity correction [OPC] design processes
• CPC Class Codes: G03F 1/70 Adapting basic layout or design of masks to lithographic process requirements, e.g., second iteration correction of mask patterns for imaging
• CPC Class Codes: H01J 2237/334 Etching
• CPC Class Codes: H01J 37/32009 Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources plasma generation in general H05H1/24
• CPC Class Codes: H01J 37/3244 Gas supply means
• CPC Class Codes: H01L 21/027 Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 photographic masks or originals per se G03F1/00; registration or positioning of photographic masks or originals G03F9/00; photographic cameras G03B; control of position G05D3/00

Abstract

Disclosed are methods of generating a proximity-corrected design layout for photoresist to be used in an etch operation. The methods may include identifying a feature in an initial design layout, and estimating one or more quantities characteristic of an in-feature plasma flux (IFPF) within the feature during the etch operation. The methods may further include estimating a quantity characteristic of an edge placement error (EPE) of the feature by comparing the one or more quantities characteristic of the IFPF to those in a look-up table (LUT, and/or through application of a multivariate model trained on the LUT, e.g., constructed through machine learning methods (MLM)) which associates values of the quantity characteristic of EPE with values of the one or more quantities characteristics of the IFPF. Thereafter, the initial design layout may be modified based on at the determined quantity characteristic of EPE.

Claims

1. A method of determining a layout of a lithography mask for an integrated circuit fabrication etch process, the method comprising:

(a) receiving a starting lithography mask layout for a feature to be etched in a partially fabricated integrated circuit;

(b) obtaining an in-feature plasma flux condition for at least one location within the feature to be etched or within an opening in the mask over the feature, wherein the in-feature plasma flux condition is predicted to be produced during the integrated circuit fabrication etch process;

(c) identifying an in-feature edge placement error for the feature by applying the plasma flux condition to a lookup table or a model that provides predictions of in-feature edge placement error caused by the integrated circuit fabrication etch process within the feature, wherein applying the plasma flux condition to the lookup table or the model identifies one or more putative values of in-feature edge placement error that correspond to the in-feature plasma flux condition; and

(d) modifying a position of the starting lithography mask layout for the feature to compensate for the in-feature edge placement error identified in (c) by applying the plasma flux condition to the look up table or the model.

2. The method of claim 1, wherein the starting lithography mask layout was produced by an optical proximity correction process.

3. The method of claim 1, wherein modifying the position of the starting lithography mask layout comprises providing the in-feature edge placement error identified in (c) to an optical proximity correction process.

4. The method of claim 1, further comprising calculating the in-feature plasma flux condition using process conditions expected to be produced in a plasma reactor where the integrated circuit fabrication etch process is to be performed.

5. The method of claim 4, wherein the calculating the in-feature plasma flux condition comprises applying the process conditions to a compact physical model.

6. The method of claim 5, wherein the compact physical model is configured to account for loading caused by features on the integrated circuit and/or visibility to plasma within the feature.

7. The method of claim 1, wherein obtaining the in-feature plasma flux condition obtains in-feature plasma flux conditions for a plurality of locations within the feature or within the opening in the mask, and

further comprising applying the in-feature plasma flux conditions for the plurality of locations to the lookup table or the model.

8. The method of claim 7, wherein the lookup table or the model is configured to identify the one or more putative values of in-feature edge placement error that correspond to the in-feature plasma flux conditions for the plurality of locations.

9. The method of claim 1, wherein applying the in-feature plasma flux condition to the lookup table or the model identifies a plurality of putative values of edge placement error.

10. The method of claim 9, further comprising interpolating between the plurality of putative values of edge placement error to provide the in-feature edge placement error identified by applying the in-feature plasma flux condition to the lookup table or the model in (d).

11. The method of claim 1, further comprising, after (c) and before (d), determining a profile of the feature to be etched from the in-feature edge placement error identified in (c);

using the profile to obtain an updated in-feature plasma flux condition; and

applying the updated in-feature plasma flux condition to the lookup table or the model to obtain an updated in-feature edge placement error,

wherein modifying the position of the starting mask layout in (d) comprises compensating for the updated edge placement error.

12. The method of claim 1, wherein the method of determining a layout is performed in two or more time steps, each representing a portion of the integrated circuit fabrication etch process, wherein (a)-(c) are performed for an initial time step of the integrated circuit fabrication etch process;

and

further comprising determining a profile of the feature to be etched at the end of the initial time step of the integrated circuit fabrication etch process, and

applying the profile of the feature to repeat operations (a)-(c) for a subsequent time step of the integrated circuit fabrication etch process,

wherein modifying the position of the starting mask layout in (d) comprises compensating for the in-feature edge placement error identified for the subsequent time step of the integrated circuit fabrication etch process.

13. A computer system for determining a layout of a lithography mask for an integrated circuit fabrication etch process, the system comprising:

one or more processors, and

a memory, the memory storing computer-readable instructions for execution on the one or more processors, including instructions for;

(a) receiving a starting lithography mask layout for a feature to be etched in a partially fabricated integrated circuit;

(b) obtaining an in-feature plasma flux condition for at least one location within the feature to be etched or within an opening in the mask over the feature, wherein the in-feature plasma flux condition is predicted to be produced during the integrated circuit fabrication etch process;

(c) identifying an in-feature edge placement error for the feature by applying the plasma flux condition to a lookup table or a model that provides predictions of in-feature edge placement error caused by the integrated circuit fabrication etch process within the feature, wherein applying the plasma flux condition to the lookup table or the model identifies one or more putative values of in-feature edge placement error that correspond to the in-feature plasma flux condition; and

(d) modifying a position of the starting lithography mask layout for the feature to compensate for the in-feature edge placement error identified in (c) by applying the plasma flux condition to the look up table or the model.

14. The computer system of claim 13, wherein instructions for receiving the starting lithography design layout in (a) comprise instructions for receiving the starting lithography design layout from a computer-readable medium;

and

wherein the computer-readable instructions stored in the memory for execution on the processor further include instructions for;

(e) writing the modified lithography mask layout from (d) to the computer-readable medium.

15. The computer system of claim 13, wherein the instructions for receiving the starting lithography mask layout comprise instructions for receiving the starting lithography mask layout produced by an optical proximity correction process.

16. The computer system of claim 13, wherein the instructions for modifying the position of the starting lithography mask layout comprise instructions for providing the in-feature edge placement error identified in (c) to an optical proximity correction process.

17. The computer system of claim 13, further comprising instructions for calculating the in-feature plasma flux condition using process conditions expected to be produced in a plasma reactor where the integrated circuit fabrication etch process is to be performed.

18. The computer system of claim 17, wherein the instructions for calculating the in-feature plasma flux condition comprise instructions for applying the process conditions to a compact physical model.

19. The computer system of claim 18, wherein the compact physical model is configured to account for loading caused by features on the integrated circuit and/or visibility to plasma within the feature.

20. The computer system of claim 13, wherein the instructions for obtaining the in-feature plasma flux condition comprise instructions for obtaining in-feature plasma flux conditions for a plurality of locations within the feature or within the opening in the mask, and

further comprising instructions for applying the in-feature plasma flux conditions for the plurality of locations to the lookup table or the model.

21. The computer system of claim 20, wherein the lookup table or the model is configured to identify the one or more putative values of in-feature edge placement error that correspond to the in-feature plasma flux conditions for the plurality of locations.

22. The computer system of claim 13, wherein the instructions for applying the in-feature plasma flux condition to the lookup table or the model comprise instructions for identifying a plurality of putative values of edge placement error.

23. The computer system of claim 22, further comprising instructions for interpolating between the plurality of putative values of edge placement error to provide the in-feature edge placement error identified by the instructions for applying the in-feature plasma flux condition to the lookup table or the model in (d).

24. The computer system of claim 13, further comprising the following instructions for execution after the instructions for (c) and before the instructions for (d):

determining a profile of the feature to be etched from the in-feature edge placement error identified in (c);

using the profile to obtain an updated in-feature plasma flux condition; and

applying the updated in-feature plasma flux condition to the lookup table or the model to obtain an updated in-feature edge placement error,

wherein the instructions for modifying the position of the starting mask layout in (d) comprise instructions for compensating for the updated edge placement error.

25. The computer system of claim 13, wherein instructions (a)-(c) are performed for an initial time step of the integrated circuit fabrication etch process;

and

further comprising instructions for

determining a profile of the feature to be etched at the end of the initial time step of the integrated circuit fabrication etch process, and

applying the profile of the feature to repeat execution of instructions (a)-(c) for a subsequent time step of the integrated circuit fabrication etch process,

wherein the instructions for modifying the position of the starting mask layout in (d) comprise instructions for compensating for the in-feature edge placement error identified for the subsequent time step of the integrated circuit fabrication etch process.

26. A system for etching semiconductor substrates, the system comprising:

the computer system of claim 13;

a photolithography module configured to;

receive the modified lithography mask layout from (d) from the computer system;

form a mask from the modified lithography mask layout from (d); and

perform a photolithography operation using the mask to transfer a layer of photoresist to a semiconductor substrate; and

a plasma-etcher configured to generate a plasma which contacts the semiconductor substrate and etches those portions of the substrate surface not covered with photoresist transferred by the photolithography module.