TRANSMISSION APPARATUS, ELECTRONIC DEVICE, AND ACTIVATION CONTROL METHOD
First Claim
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1. A transmission apparatus comprising:
- a processor thatmonitors a first operational status of processors,activates one of unactivated processors of the processors, and based on a second operational status of the activated processor, determines an activation timing of a next processor to activate next, andactivates the next processor at the activation timing.
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Abstract
An apparatus includes a processor that monitors a first operational status of processors, activates one of unactivated processors of the processors, and based on a second operational status of the activated processor, determines an activation timing of a next processor to activate next, and activates the next processor at the activation timing.
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Citations
13 Claims
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1. A transmission apparatus comprising:
a processor that monitors a first operational status of processors, activates one of unactivated processors of the processors, and based on a second operational status of the activated processor, determines an activation timing of a next processor to activate next, and activates the next processor at the activation timing. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. An electronic device comprising:
a processor that monitors a first operational status of processors, provided inside the electronic device, that execute certain data processing, activates one of unactivated processors of the processors, and based on a second operational status of the activated processor, determines an activation timing of a next processor to activate next, and activates the next processor at the activation timing.
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13. A method that executes processing repeatedly, comprising:
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monitoring a first operational status of processors, provided inside an apparatus, that execute certain data processing with respect to a transmission signal, activating one of unactivated processors of the processors, and based on a second operational status of the activated processor, determining an activation timing of a next processor to activate next, and activating the next processor at the activation timing.
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Specification