SYSTEM, CONTROL APPARATUS AND CONTROL METHOD FOR DISTRIBUTED VIDEO DISPLAY

• US 20180314483A1
• Filed: 07/19/2017
• Published: 11/01/2018
• Est. Priority Date: 04/26/2017
• Status: Active Grant

• Current Assignee: VIA Technologies Incorporated (VIA Technologies)
• Original Assignee: VIA Technologies Incorporated (VIA Technologies)
• Inventors: Liu, Steve Shu
• Granted Patent: US 10,613,812 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 3/1446 display composed of modules, e.g. video walls
• CPC Class Codes: G09G 2300/026 Video wall, i.e. juxtaposition of a plurality of screens to create a display screen of bigger dimensions
• CPC Class Codes: G09G 2370/022 Centralised management of display operation, e.g. in a server instead of locally
• CPC Class Codes: G09G 3/20 for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
• CPC Class Codes: G09G 3/3406 Control of illumination source illumination devices structurally associated with liquid crystal cells G02F1/1336
• CPC Class Codes: G09G 5/12 Synchronisation between the display unit and other units, e.g. other display units, video-disc players
• CPC Class Codes: G09G 5/18 Timing circuits for raster scan displays specially adapted for television H04N ; synchronisation between the display unit and other display units, videodisc player G09G5/12
• CPC Class Codes: H04N 21/4122 additional display device, e.g. video projector digital output for controlling a plurality of local displays G06F3/1423
• CPC Class Codes: H04N 5/268 Signal distribution or switching

Abstract

A system, a control apparatus and a control method for distributed video display are provided. The system includes an image source device configured to provide image data, a plurality of displays, a plurality of display chips respectively coupled to the displays and connected with the video source device through a network, and a control apparatus connected with the image source device and the display chips through the network and configured to transmit a playback signal to each of the display chips to control the display chips to receive the image data from the image source device and convert the received image data into display frames capable of being played by the displays. The control apparatus further transmits a synchronizing signal to each display chip to control the display chips to synchronize the clocks with each other according to the synchronizing signal and sets each of the display chips with a fixed delay time after receiving the image data to synchronously play the display frames on the displays.

Claims

1. A system for distributed video display, comprising:

an image source device, providing image data;

a plurality of displays;

a plurality of display chips, respectively coupled to the displays and connected with the image source device through a network; and

a control apparatus, connected with the image source device and the display chips through the network, transmitting a playback signal to each of the display chips so as to control the display chips to receive the image data from the image source device and converting the image data into display frames capable of being displayed by the displays, wherein

the control apparatus further transmits a synchronizing signal to each of the display chips so as to control the display chips to synchronize clocks with each other according to the synchronizing signal and sets each of the display chips with a fixed delay time after receiving the image data to synchronously play the display frames on the displays.

2. The system according to claim 1, wherein each of the display chips further resets a vertical synchronizing (vSync) signal for playing the display frames by using a register in a display interface unit (DIU) in the fixed delay time or before the fixed delay time.

3. The system according to claim 1, wherein

the control apparatus transmits a synchronizing message to each of the display chips, wherein the synchronizing message comprises a first timestamp of a time when the control apparatus transmitting the synchronizing message;

each of the display chips receives the synchronizing message, records a second timestamp of receiving the synchronizing message and after a first delay time, transmits a delay request message to the control apparatus and records a third timestamp of transmitting the delay request message;

the control apparatus receives the delay request message and transmits a delayed response message to each of the display chips, wherein the delayed response message comprises a fourth timestamp of a time when the control apparatus receives the delay request message; and

each of the display chips calculates a time offset of the clock thereof with respect to a clock of the control apparatus according to the first timestamp, the second timestamp, the third timestamp and the fourth timestamp.

4. The system according to claim 1, wherein

the control apparatus transmits a synchronizing message to each of the display chips and after transmitting the synchronizing message, transmits a continuation message recording a first timestamp of a time when the control apparatus transmits the synchronizing message to each of the display chips;

each of the display chips receives the synchronizing message, records a second timestamp of receiving the synchronizing message and after a first delay time, transmits a delay request message to the control apparatus and records a third timestamp of transmitting the delay request message;

the control apparatus receives the delay request message and transmits a delayed response message to each of the display chips, wherein the delayed response message comprises a fourth timestamp of a time when the control apparatus receives the delay request message; and

each of the display chips calculates a time offset of the clock thereof with respect to a clock of the control apparatus according to the first timestamp, the second timestamp, the third timestamp and the fourth timestamp.

5. The system according to claim 1, wherein the control apparatus transmits the synchronizing signal to each of the display chips per a predetermined time so as to control the display chips to synchronize the clocks with each other according to the synchronizing signal.

6. The system according to claim 1, wherein the control apparatus transmits the synchronizing signal to each of the display chips after the playback of the display frames of the image data ends and before display frames of a next image data are played, so as to control the display chips to synchronize the clocks with each other according to the synchronizing signal.

7. The system according to claim 1, wherein the control apparatus further determines the fixed delay time according to a time period required from a time of each of the display chips receiving the image data to a time of the image data being converted into the display frames.

8. The system according to claim 1, wherein the control apparatus is connected with each of the display chips through a wireless local network established by using an IEEE 802.1 AS protocol or through an Ethernet.

9. A control apparatus for distributed video display, comprising:

a clock;

a communication module, connected with an image source device and a plurality of display chips through a network, transmitting a playback signal to each of the display chips respectively connected with a plurality of displays; and

a processor, coupled to the clock and the communication module, controlling the display chips to receive image data from the image source device and convert the image data into display frames capable of being displayed by the displays, wherein

the processor further transmits a synchronizing signal of the clock to each of the display chips through the communication module so as to control the display chips to synchronize clocks with each other according to the synchronizing signal and sets each of the display chips with a fixed delay time after receiving the image data to synchronously play the display frames on the displays.

10. The control apparatus according to claim 9, wherein

the processor transmits a synchronizing message of the clock to each of the display chips through the communication module, and the synchronizing message comprises a first timestamp of a time when the processor transmits the synchronizing message, wherein each of the display chips receives the synchronizing message, records a second timestamp of receiving the synchronizing message and after a first delay time, transmits a delay request message to the control apparatus and records a third timestamp of transmitting the delay request message;

the processor receives the delay request message through the communication module and transmits a delayed response message to each of the display chips, wherein the delayed response message comprises a fourth timestamp of a time when the control apparatus receives the delay request message.

11. The control apparatus according to claim 9, wherein

the processor transmits a synchronizing message to each of the display chips through the communication module and after transmitting the synchronizing message through the communication module, transmits a continuation message recording a first timestamp of a time when the processor transmits the synchronizing message to each of the display chips, wherein each of the display chips receives the synchronizing message, records a second timestamp of receiving the synchronizing message and after a first delay time, transmits a delay request message to the control apparatus and records a third timestamp of transmitting the delay request message;

and

the processor receives the delay request message through the communication module and transmits a delayed response message to each of the display chips, wherein the delayed response message comprises a fourth timestamp of a time when the control apparatus receives the delay request message.

12. The control apparatus according to claim 9, wherein the processor transmits the synchronizing signal to each of the display chips through the communication module per a predetermined time, or after the playback of the display frames of the image data ends and before display frames of a next image data are played, so as to control the display chips to synchronize the clocks with each other according to the synchronizing signal.

13. The control apparatus according to claim 9, wherein the processor further determines the fixed delay time according to a time period required from a time of each of the display chips receiving the image data to a time of the image data being converted into the display frames.

14. The control apparatus according to claim 9, wherein the communication module is connected with each of the display chips through a wireless local network established by using an IEEE 802.1 AS protocol or through an Ethernet.

15. A control method for distributed video display, applicable to a control apparatus for controlling a plurality of display chips to synchronously play display frames on a plurality of corresponding displays, the method comprising:

transmitting a synchronizing signal to each of the display chips by the control apparatus, so as to control the display chips to synchronize clocks with each other according to the synchronizing signal; and

setting each of the display chips with a fixed delay time after receiving image data from an image source device on each of the display chips to synchronously play the display frames converted from the image data on the corresponding displays by the control apparatus.

16. The control method according to claim 15, wherein the step of setting each of the display chips with the fixed delay time after receiving the image data from the image source device on each of the display chips to synchronously play the display frames converted from the image data on the corresponding displays by the control apparatus further comprises:

setting each of the display chips to reset a vertical synchronizing (vSync) signal for playing the display frames by using a register in a display interface unit (DIU) in the fixed delay time or before the fixed delay time.

17. The control method according to claim 15, wherein the step of transmitting the synchronizing signal to each of the display chips by the control apparatus so as to control the display chips to synchronize the clocks with each other according to the synchronizing signal comprises:

by the control apparatus, transmitting a synchronizing message to each of the display chips, wherein the synchronizing message comprises a first timestamp of a time when the control apparatus transmitting the synchronizing message;

by each of the display chips, receiving the synchronizing message, recording a second timestamp of receiving the synchronizing message and after a first delay time, transmitting a delay request message to the control apparatus and recording a third timestamp of transmitting the delay request message;

by the control apparatus, receiving the delay request message and transmitting a delayed response message to each of the display chips, wherein the delayed response message comprises a fourth timestamp of a time when the control apparatus receives the delay request message; and

by each of the display chips, calculating a time offset of the clock of each of the display chips with respect to a clock of the control apparatus according to the first timestamp, the second timestamp, the third timestamp and the fourth timestamp.

18. The control method according to claim 15, wherein the step of transmitting the synchronizing signal to each of the display chips by the control apparatus so as to control the display chips to synchronize with each other according to the synchronizing signal comprises:

by the control apparatus, transmitting a synchronizing message to each of the display chips and after transmitting the synchronizing message, transmits a continuation message recording a first timestamp of a time when the control apparatus transmits the synchronizing message to each of the display chips;

by each of the display chips, receiving the synchronizing message, recording a second timestamp of receiving the synchronizing message and after a first delay time, transmitting a delay request message to the control apparatus and recording a third timestamp of transmitting the delay request message;

by the control apparatus, receiving the delay request message and transmitting a delayed response message to each of the display chips, wherein the delayed response message comprises a fourth timestamp of a time when the control apparatus receives the delay request message; and

by each of the display chips, calculating a time offset of the clock of each of the display chips with respect to a clock of the control apparatus according to the first timestamp, the second timestamp, the third timestamp and the fourth timestamp.

19. The control method according to claim 15, wherein the step of setting the fixed delay time after receiving the image data from the image source device on each of the display chips to synchronously play the display frames converted from the image data on the corresponding displays by the control apparatus comprises:

by the control apparatus, transmitting the synchronizing signal to each of the display chips per a predetermined time, or after the playback of the display frames of the image data ends and before display frames of a next image data are played, so as to control the display chips to synchronize the clocks with each other according to the synchronizing signal.

20. The control method according to claim 15, wherein before the step of setting each of the display chips with the fixed delay time after receiving the image data from the image source device on each of the display chips to synchronously play the display frames converted from the image data on the corresponding displays by the control apparatus, the method further comprises:

determining the fixed delay time according to a time period required from a time of each of the display chips receiving the image data to a time of the image data being converted into the display frames by the control apparatus.