PLACEMENT AND ROUTING OF CELLS USING CELL-LEVEL LAYOUT-DEPENDENT STRESS EFFECTS

• US 20180314783A1
• Filed: 04/25/2018
• Published: 11/01/2018
• Est. Priority Date: 04/28/2017
• Status: Active Grant

• Current Assignee: Synopsys Incorporated
• Original Assignee: Synopsys Incorporated
• Inventors: MOROZ, Victor
• Granted Patent: US 10,572,615 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 2119/06 Power analysis or power optimisation
• CPC Class Codes: G06F 2119/12 Timing analysis or timing optimisation
• CPC Class Codes: G06F 30/367 Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement
• CPC Class Codes: G06F 30/394 Routing G06F30/396 takes precedence
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36

Abstract

Disclosed is technology for placing cells in a circuit design layout to thereby improve the operation of place- and route equipment used for fabrication of an integrated circuit. The target cells are chosen from a cell library which includes descriptions for a plurality of cells, and information about dependency of each cell on hypothetical boundary conditions that can be imposed on the cell by any stress source originating in the vicinity of said cell in the layout. In order to select a cell for a target location in the layout, boundary conditions imposed on the target position by each of the cells neighboring the target position are determined. The system then selects an appropriate target cell in dependence upon the determined boundary conditions and the performance of the cell based on the boundary conditions imposed on the cell by the neighboring cells from the cell library.

Claims

1. A method of improving the operation of a place-and-route system in the selection of a target cell in a target circuit design layout for fabrication of an integrated circuit, comprising:

providing to a computer system a cell library describing a plurality of cells;

for placement into a target position in the target circuit design layout, a computer system selecting a target cell from the cell library in dependence upon a circuit design, the target position having one or more neighboring cells in the target circuit design layout; and

placing the target cell into the target position in the target circuit design layout,

wherein the cell library further indicates, for each cell in the cell library;

boundary conditions imposed by the cell on neighboring cells in a layout, and

dependency of performance of the cell on boundary conditions imposed on the cell by neighboring cells in a layout;

and wherein a computer system selecting the target cell from the cell library comprises;

a computer system determining from the cell library, boundary conditions imposed on the target position by each of a plurality of cells neighboring the target position in the target circuit design layout; and

a computer system selecting the target cell further in dependence upon the determined boundary conditions and the dependency, as indicated in the cell library, of performance of the target cell on boundary conditions imposed on the target cell by neighboring cells in a layout.

2. The method of claim 1, wherein the selected target cell imposes boundary conditions on a first neighboring cell of the target position in the target circuit design layout,

further comprising a computer system replacing the first neighboring cell with a second neighboring cell in dependence upon the boundary conditions imposed by the target cell on the first neighboring cell.

3. The method of claim 1, wherein a computer system selecting the target cell from the cell library further comprises taking into consideration an additional factor.

4. The method of claim 1, wherein at least two of the cells in the plurality of cells perform a common logic function.

5. The method of claim 1, wherein providing a cell library to a computer system comprises:

a computer system calculating dependency of performance of each subject cell in the cell library on boundary conditions imposed on the subject cell by neighboring cells in a layout; and

writing into the cell library in association with the subject cell an indication of the dependency.

6. The method of claim 5, wherein the subject cell includes at least one pin, at least one transistor and at least one conductor, at least one of the conductors being an interconnect, each of the interconnects having at least two endpoints, each of the endpoints being either a terminal of a transistor or a pin,

and wherein calculating dependency of performance of the subject cell in the cell library on boundary conditions imposed on the subject cell by neighboring cells in a layout comprises:

synthesizing a three-dimensional cell representation of the subject cell by simulation of a fabrication process, the three-dimensional cell representation including the transistors, pins and interconnects identified for the subject cell;

for each particular one of a plurality of different hypothetical sets of boundary conditions imposed on the subject cell, estimating, from the three-dimensional cell representation, a performance of the subject cell resulting from the particular hypothetical set of boundary conditions; and

merging the estimated performance of the subject cell resulting from all the hypothetical sets of boundary conditions in the step of estimating the performance.

7. The method of claim 6, wherein estimating the performance of the subject cell resulting from the particular hypothetical set of boundary conditions comprises:

identifying, from a subject cell layout of the subject cell in the cell library, locations for each transistor in the subject cell and a plurality of interconnect endpoints in the subject cell;

estimating, from the three-dimensional cell representation, operational characteristics of each of the transistors in the subject cell resulting from the particular hypothetical set of boundary conditions imposed on the subject cell;

developing an annotated netlist that includes each transistor in the subject cell identified from the subject cell layout, and each of the interconnects identified from the subject cell layout, and which further indicates the operational characteristics of each of the transistors in the subject cell resulting from the particular hypothetical set of boundary conditions imposed on the subject cell; and

applying the annotated netlist in a circuit simulator.

8. The method of claim 7, wherein estimating, from the three-dimensional cell representation, the operational characteristics of each of the transistors in the subject cell resulting from the particular hypothetical set of boundary conditions imposed on the subject cell comprises:

calculating a stress profile the three-dimensional cell representation of the subject cell in at least two dimensions with the particular hypothetical set of boundary conditions imposed on the subject cell acting as boundary conditions of the stress profile;

dividing the three-dimensional cell representation into a plurality of three-dimensional simulation domains, each including one of the transistors of the three-dimensional cell representation and a domain-specific stress profile; and

estimating the operational characteristics of each given one of the transistors in the subject cell resulting from the domain-specific stress profile in the simulation domain that includes the given transistor.

9. The method of claim 8, wherein estimating the operational characteristics of the given transistor comprises:

determining, from the domain-specific stress profile, stress components at at least one point in a channel of the given transistor; and

estimating the operational characteristics of the given transistor in dependence upon the stress components determined for the channel of the given transistor.

10. The method of claim 7 further comprising:

a computer system estimating, from the three-dimensional cell representation, parasitic resistance values between at least one pair of the interconnect endpoints which share an interconnect;

a computer system estimating, from the three-dimensional cell representation, parasitic capacitance values between at least one pair of the interconnect endpoints which are pins of the circuit design; and

a computer system adding to the annotated netlist the parasitic resistance values and parasitic capacitance values estimated from the three-dimensional cell representation.

11. The method of claim 7, wherein applying the annotated netlist in a circuit simulator to evaluate the performance of the cell comprises estimating a circuit timing of the cell.

12. The method of claim 7, wherein applying the annotated netlist in a circuit simulator to evaluate the performance of the cell comprises estimating power consumed by the cell.

13. The method of claim 7, further comprising, estimating, from the three-dimensional cell representation, operational characteristics of every transistor in the three-dimensional cell representation.

14. The method of claim 7, wherein estimating the operational characteristics of each of the transistors in the subject cell resulting from the particular hypothetical set of boundary conditions imposed on the subject cell comprises:

estimating current-voltage characteristics of each given one of the transistors resulting from the particular hypothetical set of boundary conditions imposed on the subject cell; and

converting the current-voltage characteristics of each given transistor into a respective set of model parameters for a transistor model.

15. The method of claim 14, wherein the transistor model is a Berkeley Short-channel Insulated-gate field-effect transistor Model (BSIM).

16. A system for improving the operation of a place-and-route equipment in the selection of a target cell in a target circuit design layout for fabrication of an integrated circuit, the system comprising a memory and a data processor coupled to the memory, the data processor configured to:

provide to a computer system a cell library describing a plurality of cells;

for placement into a target position in the target circuit design layout, select a target cell from the cell library in dependence upon a circuit design, the target position having one or more neighboring cells in the target circuit design layout; and

place the target cell into the target position in the target circuit design layout,

wherein the cell library further indicates, for each cell in the cell library;

boundary conditions imposed by the cell on neighboring cells in a layout, and

dependency of performance of the cell on boundary conditions imposed on the cell by neighboring cells in a layout;

and wherein in selecting the target cell from the cell library the data processor is configured to;

determine from the cell library, boundary conditions imposed on the target position by each of a plurality of cells neighboring the target position in the target circuit design layout; and

select the target cell further in dependence upon the determined boundary conditions and the dependency, as indicated in the cell library, of performance of the target cell on boundary conditions imposed on the target cell by neighboring cells in a layout.

17. The system of claim 16, wherein the selected target cell imposes boundary conditions on a first neighboring cell of the target position in the target circuit design layout,

and wherein the data processor is further configured to replace the first neighboring cell with a second neighboring cell in dependence upon the boundary conditions imposed by the target cell on the first neighboring cell.

18. The system of claim 16, wherein in selecting the target cell from the cell library, the system further takes an additional factor into consideration.

19. The system of claim 16, wherein at least two of the cells in the plurality of cells perform a common logic function.

20. The system of claim 16, wherein in providing a cell library, the system:

calculates dependency of performance of each subject cell in the cell library on boundary conditions imposed on the subject cell by neighboring cells in a layout; and

writes into the cell library in association with the subject cell an indication of the dependency.

21. The system of claim 20, wherein the subject cell includes at least one pin, at least one transistor and at least one conductor, at least one of the conductors being an interconnect, each of the interconnects having at least two endpoints, each of the endpoints being either a terminal of a transistor or a pin,

and wherein in calculating dependency of performance of the subject cell in the cell library on boundary conditions imposed on the subject cell by neighboring cells in a layout, the system:

synthesizes a three-dimensional cell representation of the subject cell by simulation of a fabrication process, the three-dimensional cell representation including the transistors, pins and interconnects identified for the subject cell;

for each particular one of a plurality of different hypothetical sets of boundary conditions imposed on the subject cell, estimates, from the three-dimensional cell representation, a performance of the subject cell resulting from the particular hypothetical set of boundary conditions; and

merges the estimated performance of the subject cell resulting from all the hypothetical sets of boundary conditions in the step of estimating the performance.

22. The system of claim 21, wherein in estimating the performance of the subject cell resulting from the particular hypothetical set of boundary conditions, the system:

identifies, from a subject cell layout of the subject cell in the cell library, locations for each transistor in the subject cell and a plurality of interconnect endpoints in the subject cell;

estimates, from the three-dimensional cell representation, operational characteristics of each of the transistors in the subject cell resulting from the particular hypothetical set of boundary conditions imposed on the subject cell;

develops an annotated netlist that includes each transistor in the subject cell identified from the subject cell layout, and each of the interconnects identified from the subject cell layout, and which further indicates the operational characteristics of each of the transistors in the subject cell resulting from the particular hypothetical set of boundary conditions imposed on the subject cell; and

applies the annotated netlist in a circuit simulator.

23. The system of claim 22, wherein in estimating, from the three-dimensional cell representation, the operational characteristics of each of the transistors in the subject cell resulting from the particular hypothetical set of boundary conditions imposed on the subject cell, the system:

calculates a stress profile the three-dimensional cell representation of the subject cell in at least two dimensions with the particular hypothetical set of boundary conditions imposed on the subject cell acting as boundary conditions of the stress profile;

divides the three-dimensional cell representation into a plurality of three-dimensional simulation domains, each including one of the transistors of the three-dimensional cell representation and a domain-specific stress profile; and

estimates the operational characteristics of each given one of the transistors in the subject cell resulting from the domain-specific stress profile in the simulation domain that includes the given transistor.

24. The system of claim 23, wherein in estimating the operational characteristics of the given transistor, the system:

determines, from the domain-specific stress profile, stress components at least one point in a channel of the given transistor; and

estimates the operational characteristics of the given transistor in dependence upon the stress components determined for the channel of the given transistor.

25. The system of claim 22, wherein in estimating the performance of the subject cell resulting from the particular hypothetical set of boundary conditions, the system further:

estimates, from the three-dimensional cell representation, parasitic resistance values between at least one pair of the interconnect endpoints which share an interconnect;

estimates, from the three-dimensional cell representation, parasitic capacitance values between at least one pair of the interconnect endpoints which are pins of the circuit design; and

adds to the annotated netlist the parasitic resistance values and parasitic capacitance values estimated from the three-dimensional cell representation.

26. The system of claim 22, wherein the evaluation of the performance of the cell comprises estimating a circuit timing of the cell.

27. The system of claim 22, wherein the evaluation of the performance of the cell comprises estimating power consumed by the cell.

28. The system of claim 22, wherein the system estimates, from the three-dimensional cell representation, operational characteristics of every transistor in the three-dimensional cell representation.

29. The system of claim 22, wherein in estimating the operational characteristics of each of the transistors in the subject cell resulting from the particular hypothetical set of boundary conditions imposed on the subject cell, the system:

estimates current-voltage characteristics of each given one of the transistors resulting from the particular hypothetical set of boundary conditions imposed on the subject cell; and

converts the current-voltage characteristics of each given transistor into a respective set of model parameters for a transistor model.

30. The system of claim 29, wherein the transistor model is a Berkeley Short-channel Insulated-gate field-effect transistor Model (BSIM).

31. A non-transitory computer readable medium, for use with a cell library describing a plurality of cells, which indicates, for each cell in the cell library:

boundary conditions imposed by the cell on neighboring cells in a layout; and

dependency of performance of the cell on boundary conditions imposed on the cell by neighboring cells in a layout,

the computer readable medium having stored thereon a plurality of instructions which when executed by a processor cause the processor to;

select, for placement into a target position in the target circuit design layout, a target cell from the cell library in dependence upon a circuit design, the target position having one or more neighboring cells in the target circuit design layout; and

place the target cell into the target position in the target circuit design layout,

wherein in selecting the target cell from the cell library the processor;

determines from the cell library, boundary conditions imposed on the target position by each of a plurality of cells neighboring the target position in the target circuit design layout; and

selects the target cell further in dependence upon the determined boundary conditions and the dependency, as indicated in the cell library, of performance of the target cell on boundary conditions imposed on the target cell by neighboring cells in a layout.

32. The non-transitory computer readable medium of claim 31, wherein the selected target cell imposes boundary conditions on a first neighboring cell of the target position in the target circuit design layout,

and wherein the plurality of instructions further cause the processor to replace the first neighboring cell with a second neighboring cell in dependence upon the boundary conditions imposed by the target cell on the first neighboring cell.

33. The non-transitory computer readable medium of claim 31, wherein selecting the target cell from the cell library further takes into consideration an additional factor.

34. The non-transitory computer readable medium of claim 31, wherein at least two of the cells in the plurality of cells perform a common logic function.

35. A system for improving the operation of a place-and-route equipment in the placement of target cells in a target circuit design layout for fabrication of an integrated circuit, the system comprising a memory and a data processor coupled to the memory, the data processor configured to:

calculate dependency of performance of each subject cell in a cell library on boundary conditions imposed on the subject cell by neighboring cells in a layout;

write into the cell library in association with the subject cell an indication of the dependency; and

forward the cell library toward a user for use by the place-and-route equipment.

36. A non-transitory computer readable medium, for use in improving the operation of a place-and-route system in the placement of target cells in a target circuit design layout for fabrication of an integrated circuit,

the medium having stored thereon a cell library describing a plurality of cells, the cell library indicating, for each cell in the cell library:

boundary conditions imposed by the cell on neighboring cells in a layout; and

dependency of performance of the cell on boundary conditions imposed on the cell by neighboring cells in a layout.