DISPLAY PANEL, DRIVING METHOD FOR DISPLAY PANEL, AND DISPLAY DEVICE

• US 20180315367A1
• Filed: 08/28/2017
• Published: 11/01/2018
• Est. Priority Date: 04/08/2015
• Status: Active Grant

• Current Assignee: Beijing BOE Optoelectronics Technology Co Ltd. (BOE Technology Group Co., Ltd.), BOE Technology Group Co., Ltd.
• Original Assignee: Beijing BOE Optoelectronics Technology Co Ltd. (BOE Technology Group Co., Ltd.), BOE Technology Group Co., Ltd.
• Inventors: YANG, Ming, DONG, Xue, CHEN, Xiaochuan, XU, Rui, WANG, Lei, WANG, Qian, LIU, Peng, LU, Pengcheng
• Granted Patent: US 10,255,840 B2
• Time in Patent Office: Days
• CPC Class Codes: G02F 1/1362 Active matrix addressed cells G02F1/134336, G02F1/134363 take precedence
• CPC Class Codes: G09G 2300/0408 Integration of the drivers onto the display substrate
• CPC Class Codes: G09G 2300/0804 Sub-multiplexed active matrix panel, i.e. wherein one active driving circuit is used at pixel level for multiple image producing elements
• CPC Class Codes: G09G 2310/0297 Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns
• CPC Class Codes: G09G 3/20 for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
• CPC Class Codes: G09G 3/2003 Display of colours specific for liquid crystal displays G09G3/3607
• CPC Class Codes: G09G 3/2085 Special arrangements for addressing the individual elements of the matrix, other than by driving respective rows and columns in combination
• CPC Class Codes: G09G 3/22 using controlled light sources
• CPC Class Codes: G09G 3/3648 using an active matrix G09G3/367 - G09G3/3696 take precedence

Abstract

A display panel, a method for driving the display panel, and a display device are provided. The display panel includes a display region and a peripheral region surrounding the display region. Multiple gate lines each extending in a first direction and multiple data lines each extending in a second direction are arranged at the display region. A multiplexer is arranged at the peripheral region. The multiplexer is used to, under the control of gate line ON signals from a gate line switching control line, input gate line signals from a source driver unit to corresponding gate lines, and under the control of data line ON signals from corresponding data line switching control lines, input data signals from the source driver unit to corresponding data lines.

Claims

1. A display panel, comprising a display region and a peripheral region surrounding the display region, a plurality of gate lines each extending in a first direction and a plurality of data lines each extending in a second direction being arranged at the display region,

wherein a multiplexer is arranged at the peripheral region, signal input ends of the multiplexer are coupled to output ends of a source driver unit according to a one-to-one correspondence, first kind output ends of the multiplexer are coupled to the data lines according to a one-to-one correspondence, second kind output ends of the multiplexer are coupled to the gate lines according to a one-to-one correspondence, first kind control ends of the multiplexer are coupled to data line switching control lines according to a one-to-one correspondence, and a second kind control end of the multiplexer is coupled to a gate line switching control line;

and

the multiplexer is configured to, under the control of gate line ON signals from the gate line switching control line, input gate line signals output by the source driver unit to corresponding gate lines, and under the control of data line ON signals from corresponding data line switching control lines, input data signals from the source driver unit to corresponding data lines.

2. The display panel according to claim 1, wherein the multiplexer comprises first kind switching transistors corresponding to the data lines respectively, and second kind switching transistors corresponding to the gate lines respectively;

wherein drain electrodes of the first kind switching transistors are respectively coupled to the data lines, source electrodes thereof are respectively coupled to the output ends of the source driver unit, and gate electrodes thereof are respectively coupled to the data line switching control lines; and

drain electrodes of the second kind switching transistors are respectively coupled to the gate lines, source electrodes thereof are respectively coupled to the output ends of the source driver unit, and gate electrodes thereof are coupled to the gate line switching control line.

3. The display panel according to claim 2, wherein a number of the first kind control ends of the multiplexer is identical to a number of subpixels in each pixel at the display region, and a number of the signal input ends of the multiplexer is identical to a number of columns of pixels at the display region.

4. The display panel according to claim 3, wherein the number of the signal input ends of the multiplexer is identical to a number of the gate lines.

5. The display panel according to claim 4, wherein the multiplexer comprises a plurality of sub-multiplexers corresponding to the columns of pixels at the display region respectively, and

each sub-multiplexer comprises the first kind switching transistors at an amount identical to columns of subpixels in each column of pixels, and one second kind switching transistor.

6. The display panel according to claim 1, wherein gate voltage storage capacitors are further arranged at the display region, and the gate voltage storage capacitors respectively couple the second kind output ends of the multiplexer to corresponding gate lines.

7. The display panel according to claim 6, wherein each gate voltage storage capacitor consists of a gate line and a common sub-electrode coupled to each other, and the common sub-electrode is arranged at a layer identical to common electrodes of the pixels and is separated from the common electrodes of the pixels.

8. The display panel according to claim 1, wherein the first direction is perpendicular to the second direction.

9. The display panel according to claim 2, wherein the first kind transistors and the second kind transistors are thin film transistors (TFTs) or metal-oxide semiconductor field-effect transistors (MOSFETs).

10. A display device comprising the display panel according to claim 1.

11. The display panel according to claim 2, wherein gate voltage storage capacitors are further arranged at the display region, and the gate voltage storage capacitors respectively couple the second kind output ends of the multiplexer to corresponding gate lines.

12. The display panel according to claim 11, wherein each gate voltage storage capacitor consists of a gate line and a common sub-electrode coupled to each other, and the common sub-electrode is arranged at a layer identical to common electrodes of the pixels and is separated from the common electrodes of the pixels.

13. The display panel according to claim 3, wherein gate voltage storage capacitors are further arranged at the display region, and the gate voltage storage capacitors respectively couple the second kind output ends of the multiplexer to corresponding gate lines.

14. The display panel according to claim 13, wherein each gate voltage storage capacitor consists of a gate line and a common sub-electrode coupled to each other, and the common sub-electrode is arranged at a layer identical to common electrodes of the pixels and is separated from the common electrodes of the pixels.

15. The display panel according to claim 4, wherein gate voltage storage capacitors are further arranged at the display region, and the gate voltage storage capacitors respectively couple the second kind output ends of the multiplexer to corresponding gate lines.

16. The display panel according to claim 15, wherein each gate voltage storage capacitor consists of a gate line and a common sub-electrode coupled to each other, and the common sub-electrode is arranged at a layer identical to common electrodes of the pixels and is separated from the common electrodes of the pixels.

17. The display panel according to claim 5, wherein gate voltage storage capacitors are further arranged at the display region, and the gate voltage storage capacitors respectively couple the second kind output ends of the multiplexer to corresponding gate lines.

18. The display panel according to claim 17, wherein each gate voltage storage capacitor consists of a gate line and a common sub-electrode coupled to each other, and the common sub-electrode is arranged at a layer identical to common electrodes of the pixels and is separated from the common electrodes of the pixels.