PIXEL CIRCUIT, DISPLAY PANEL, DISPLAY DEVICE AND DRIVING METHOD

• US 20180315374A1
• Filed: 04/17/2017
• Published: 11/01/2018
• Est. Priority Date: 08/22/2016
• Status: Active Grant

• Current Assignee: BOE Technology Group Co., Ltd., Ordos Yuansheng Optoelectronics Co., Ltd. (BOE Technology Group Co., Ltd.)
• Original Assignee: BOE Technology Group Co., Ltd., Ordos Yuansheng Optoelectronics Co., Ltd. (BOE Technology Group Co., Ltd.)
• Inventors: ZHANG, Yi, ZHANG, Kai, XUAN, Minghua, KO, Young Yik, HUANGFU, Lujiang
• Granted Patent: US 10,692,434 B2
• Time in Patent Office: Days
• CPC Class Codes: G09G 2300/0426 Layout of electrodes and connections
• CPC Class Codes: G09G 2300/0814 used for selection purposes, e.g. logical AND for partial update
• CPC Class Codes: G09G 2300/0819 used for counteracting undesired variations, e.g. feedback or autozeroing
• CPC Class Codes: G09G 2300/0842 forming a memory circuit, e.g. a dynamic memory with one capacitor
• CPC Class Codes: G09G 2300/0861 with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
• CPC Class Codes: G09G 2310/0251 Precharge or discharge of pixel before applying new pixel voltage
• CPC Class Codes: G09G 2310/0262 The addressing of the pixel, in a display other than an active matrix LCD, involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependent on signals of two data electrodes
• CPC Class Codes: G09G 2310/08 Details of timing specific for flat panels, other than clock recovery
• CPC Class Codes: G09G 2320/0204 Compensation of DC component across the pixels in flat panels
• CPC Class Codes: G09G 2320/045 Compensation of drifts in the characteristics of light emitting or modulating elements
• CPC Class Codes: G09G 2320/0693 Calibration of display systems
• CPC Class Codes: G09G 3/3208 organic, e.g. using organic light-emitting diodes [OLED]
• CPC Class Codes: G09G 3/3233 with pixel circuitry controlling the current through the light-emitting element
• CPC Class Codes: G09G 3/3258 with pixel circuitry controlling the voltage across the light-emitting element
• CPC Class Codes: G09G 3/3266 Details of drivers for scan electrodes
• CPC Class Codes: G09G 3/3275 Details of drivers for data electrodes
• CPC Class Codes: H10K 59/131 Interconnections, e.g. wiring lines or terminals

Abstract

A pixel circuit, a display panel, a display device and a driving method. The pixel circuit includes a storage capacitor, an organic light emitting diode, a driving transistor, an emission control circuit, a reset circuit, a threshold compensation circuit, a first data write circuit, a reference voltage write circuit, and an initializing circuit.

Claims

1. A pixel circuit, comprising:

a storage capacitor including a first end connected with a first node and a second end connected with a second node;

an organic light-emitting diode (OLED) including a first electrode connected with a third node;

a driving transistor including a gate electrode connected with the first node, wherein the driving transistor is configured to control the OLED to emit light according to a voltage of the first node;

an emission control circuit configured to receive an emission control signal and control an on/off state of the OLED according to the emission control signal;

a reset circuit configured to receive a reset control signal and write a reset voltage into the first node according to the reset control signal;

a threshold compensation circuit configured to receive a first scanning signal and write a compensating voltage into the first node according to the first scanning signal, wherein the compensating voltage is a sum of a first supply voltage and a threshold voltage of the driving transistor;

a first data write circuit configured to receive the first scanning signal and a data signal and write the data signal into the second node according to the first scanning signal;

a reference voltage write circuit configured to receive a second scanning signal and write a reference voltage into the second node according to the second scanning signal; and

an initializing circuit configured to receive the first scanning signal or the reset control signal and write an initializing voltage into the third node according to the first scanning signal or the reset control signal.

2. The pixel circuit according to claim 1, wherein the initializing voltage is equal to the reset voltage.

3. The pixel circuit according to claim 1, wherein the OLED further includes a second electrode;

the second electrode of the OLED is electrically connected with a second power line to receive a second supply voltage;

the first electrode of the OLED is an anode;

the second electrode of the OLED is a cathode; and

difference between the initializing voltage and the second supply voltage is less than a cut-in voltage of the OLED.

4. The pixel circuit according to claim 3, wherein the initializing voltage is less than the second supply voltage.

5. The pixel circuit according to claim 1, wherein the reset circuit includes a first transistor;

the threshold compensation circuit includes a second transistor;

the first data write circuit includes a third transistor;

the reference voltage write circuit includes a fourth transistor;

the emission control circuit includes a fifth transistor; and

the initializing circuit includes a sixth transistor.

6. The pixel circuit according to claim 5, wherein

a gate electrode of the driving transistor is electrically connected with the first node;

a first electrode of the driving transistor is electrically connected with a first power line to receive the first supply voltage; and

a second electrode of the driving transistor is electrically connected with a fourth node;

the first electrode of the OLED is electrically connected with the third node, and a second electrode of the OLED is electrically connected with a second power line to receive a second supply voltage;

a gate electrode of the first transistor is electrically connected with a reset control signal line to receive the reset control signal;

a first electrode of the first transistor is electrically connected with a reset voltage line to receive the reset voltage; and

a second electrode of the first transistor is electrically connected with the first node;

a gate electrode of the second transistor is electrically connected with a first scanning signal line to receive the first scanning signal;

a first electrode of the second transistor is electrically connected with the first node; and

a second electrode of the second transistor is electrically connected with the fourth node;

a gate electrode of the third transistor is electrically connected with the first scanning signal line to receive the first scanning signal;

a first electrode of the third transistor is electrically connected with a data signal line to receive the data signal; and

a second electrode of the third transistor is electrically connected with the second node;

a gate electrode of the fourth transistor is electrically connected with a second scanning signal line to receive a second scanning signal;

a first electrode of the fourth transistor is electrically connected with a reference voltage line to receive the reference voltage; and

a second electrode of the fourth transistor is electrically connected with the second node;

a gate electrode of the fifth transistor is electrically connected with an emission control signal line to receive the emission control signal;

a first electrode of the fifth transistor is electrically connected with the third node; and

a second electrode of the fifth transistor is electrically connected with the fourth node; and

a gate electrode of the sixth transistor is electrically connected with the first scanning signal line or the reset control signal line to receive the first scanning signal or the reset control signal;

a first electrode of the sixth transistor is electrically connected with the reset voltage line to receive the reset voltage; and

a second electrode of the sixth transistor is electrically connected with the third node.

7. The pixel circuit according to claim 5, wherein the driving transistor, the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor and the sixth transistor are all P-type transistors.

8. The pixel circuit according to claim 5, wherein the driving transistor, the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor and the sixth transistor are all thin-film transistors (TFTs).

9. The pixel circuit according to claim 1, further comprising a second data write circuit configured to receive the reset control signal and the data signal and write the data signal into the second node according to the reset control signal.

10. The pixel circuit according to claim 9, wherein the reset circuit includes a first transistor;

the threshold compensation circuit includes a second transistor;

the first data write circuit includes a third transistor;

the reference voltage write circuit includes a fourth transistor;

the emission control circuit includes a fifth transistor;

the initializing circuit includes a sixth transistor; and

the second data write circuit includes a seventh transistor.

11. The pixel circuit according to claim 10, wherein

a gate electrode of the driving transistor is electrically connected with the first node;

a first electrode of the driving transistor is electrically connected with a first power line to receive the first supply voltage; and

a second electrode of the driving transistor is electrically connected with a fourth node;

the first electrode of the OLED is electrically connected with the third node, and a second electrode of the OLED is electrically connected with a second power line to receive a second supply voltage;

a gate electrode of the first transistor is electrically connected with a reset control signal line to receive the reset control signal;

a first electrode of the first transistor is electrically connected with a reset voltage line to receive the reset voltage; and

a second electrode of the first transistor is electrically connected with the first node;

a gate electrode of the second transistor is electrically connected with a first scanning signal line to receive the first scanning signal;

a first electrode of the second transistor is electrically connected with the first node; and

a second electrode of the second transistor is electrically connected with the third node;

a gate electrode of the third transistor is electrically connected with the first scanning signal line to receive the first scanning signal;

a first electrode of the third transistor is electrically connected with a data signal line to receive the data signal; and

a second electrode of the third transistor is electrically connected with the second node;

a gate electrode of the fourth transistor is electrically connected with a second scanning signal line to receive the second scanning signal;

a first electrode of the fourth transistor is electrically connected with a reference voltage line to receive the reference voltage; and

a second electrode of the fourth transistor is electrically connected with the second node;

a gate electrode of the fifth transistor is electrically connected with a emission control signal line to receive the emission control signal;

a first electrode of the fifth transistor is electrically connected with the third node; and

a second electrode of the fifth transistor is electrically connected with the fourth node;

a gate electrode of the sixth transistor is electrically connected with the first scanning signal line or the reset control signal line to receive the first scanning signal or the reset control signal;

a first electrode of the sixth transistor is electrically connected with the reset voltage line to receive the reset voltage; and

a second electrode of the sixth transistor is electrically connected with the third node; and

a gate electrode of the seventh transistor is electrically connected with the reset control signal line to receive the reset control signal;

a first electrode of the seventh transistor is electrically connected with the data signal line to receive the data signal; and

a second electrode of the seventh transistor is electrically connected with the second node.

12. The pixel circuit according to claim 10, wherein the driving transistor, the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor and the seventh transistor are all P-type transistors.

13. The pixel circuit according to claim 10, wherein the driving transistor, the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor and the seventh transistor are all TFTs.

14. A display panel, comprising the pixel circuit according to claim 1.

15. The display panel according to claim 14, further comprising:

a data driver configured to provide the data signal for the pixel circuit; and

a scan driver configured to provide the emission control signal, the first scanning signal, the second scanning signal and the reset control signal for the pixel circuit.

16. A display device, comprising the display panel according to claim 14.

17. A driving method of the pixel circuit according to claim 1, comprising a reset period, a data write and threshold compensation period, a voltage drop compensation period, and an emission period within the display period of one frame, wherein

in the reset period, the emission control signal is set to be a turn-off voltage;

the reset control signal is set to be a turn-on voltage;

the first scanning signal is set to be a turn-off voltage;

the second scanning signal is set to be a turn-on voltage;

the data signal is set to be an ineffective data signal;

in the data write and threshold compensation period, the emission control signal is set to be a turn-off voltage;

the reset control signal is set to be a turn-off voltage;

the first scanning signal is set to be a turn-on voltage;

the second scanning signal is set to be a turn-off voltage;

the data signal is set to be an effective data signal;

in the voltage drop compensation period, the emission control signal is set to be a turn-off voltage;

the reset control signal is set to be a turn-off voltage;

the first scanning signal is set to be a turn-off voltage;

the second scanning signal is set to be a turn-on voltage;

the data signal is set to be an ineffective data signal; and

in the emission period, the emission control signal is set to be a turn-on voltage;

the reset control signal is set to be a turn-off voltage;

the first scanning signal is set to be a turn-off voltage;

the second scanning signal is set to be a turn-on voltage; and

the data signal is set to be an ineffective data signal.

18. A driving method of the pixel circuit according to claim 9, comprising a reset period, a data write and threshold compensation period, a voltage drop compensation period and an emission period within the display period of one frame, wherein

in the reset period, the emission control signal is set to be a turn-off voltage;

the reset control signal is set to be a turn-on voltage;

the first scanning signal is set to be a turn-off voltage;

the second scanning signal is set to be a turn-off voltage;

the data signal is set to be an effective data signal;

in the data write and threshold compensation period, the emission control signal is set to be a turn-off voltage;

the reset control signal is set to be a turn-off voltage;

the first scanning signal is set to be a turn-on voltage;

the second scanning signal is set to be a turn-off voltage;

the data signal is set to be an effective data signal;

in the voltage drop compensation period, the emission control signal is set to be a turn-off voltage;

the reset control signal is set to be a turn-off voltage;

the first scanning signal is set to be a turn-off voltage;

the second scanning signal is set to be a turn-on voltage;

the data signal is set to be an ineffective data signal;

in the emission period, the emission control signal is set to be a turn-on voltage;

the reset control signal is set to be a turn-off voltage;

the first scanning signal is set to be a turn-off voltage;

the second scanning signal is set to be a turn-on voltage; and

the data signal is set to be an ineffective data signal.

20. The driving method according to claim 17, further comprising an emission continuation period within the display period of one frame, wherein

the emission continuation period includes at least one shutdown sub-period and at least one emission sub-period;

in the shutdown sub-period, the emission control signal is set to be a turn-off voltage;

the reset control signal is set to be a turn-off voltage;

the first scanning signal is set to be a turn-off voltage;

the second scanning signal is set to be a turn-on voltage;

the data signal is set to be an ineffective data signal;

in the emission sub-period, the emission control signal is set to be a turn-on voltage;

the reset control signal is set to be a turn-off voltage;

the first scanning signal is set to be a turn-off voltage;

the second scanning signal is set to be a turn-on voltage; and

the data signal is set to be an ineffective data signal.

22. The driving method according to claim 20, wherein a duration of each shutdown sub-period is equal to a sum of a duration of the reset period, a duration of the data write and threshold compensation period, and a duration of the voltage drop compensation period;

and a duration of each emission sub-period is equal to a duration of the emission period.

19. (canceled)

21. (canceled)