STORAGE SYSTEM AND METHOD FOR BAD BLOCK RECYCLING

• US 20180315487A1
• Filed: 05/01/2017
• Published: 11/01/2018
• Est. Priority Date: 05/01/2017
• Status: Active Grant

• Current Assignee: JP Morgan Chase Bank, N.A. (JP Morgan Chase & Co)
• Original Assignee: Western Digital Technologies Incorporated (Western Digital Corporation)
• Inventors: Avraham, DUDY, Zamir, Ran, Alrod, Idan, Sharon, Eran
• Granted Patent: US 10,229,751 B2
• Time in Patent Office: Days
• CPC Class Codes: G11C 16/14 Circuits for erasing electrically, e.g. erase voltage switching circuits
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
• CPC Class Codes: G11C 2029/1202 Word line control
• CPC Class Codes: G11C 29/025 in signal lines
• CPC Class Codes: G11C 29/12 Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
• CPC Class Codes: G11C 29/765 in solid state disks

Abstract

A storage system is provided comprising a controller and a memory. The controller is configured to identify at least two physical blocks of memory that are designated as bad blocks because of at least one defective wordline; identify which wordlines in the at least two physical blocks of memory are defective; and create a logical block of memory from non-defective wordlines in the at least two physical blocks of memory, wherein some portions of the logical block are mapped to one of the at least two physical blocks of memory, and wherein other portions of the logical block are mapped to another one of the at least two physical blocks of memory.

Claims

1. A storage system comprising:

a memory comprising a plurality of physical blocks of memory; and

a controller in communication with the memory, wherein the controller is configured to;

identify at least two physical blocks of memory that are designated as bad blocks because of at least one defective wordline;

identify which wordlines in the at least two physical blocks of memory are defective; and

create a logical block of memory from non-defective wordlines in the at least two physical blocks of memory, wherein some portions of the logical block are mapped to one of the at least two physical blocks of memory, and wherein other portions of the logical block are mapped to another one of the at least two physical blocks of memory.

3. The storage system of claim 1, wherein the memory comprises a plurality of memory dies organized in a plurality of planes, and wherein the at least two physical blocks of memory are from a same plane.

4. The storage system of claim 1, wherein the controller is further configured to, for each of the at least two physical blocks of memory, create the logical block by selecting wordlines up to a defective wordline area.

5. The storage system of claim 4, wherein the controller is further configured to erase wordlines subsequent to the defective wordline area in the at least two physical blocks of memory.

6. The storage system of claim 1, wherein the controller is further configured to create the logical block by selecting wordlines preceding the defective wordline area in one of the at least two physical blocks of memory and by selecting wordlines subsequent to the defective wordline area in another one of the at least two physical blocks of memory.

7. The storage system of claim 6, wherein the controller is further configured to write random data preceding the defective wordline area in the another one of the at least two physical blocks of memory.

8. The storage system of claim 1, wherein the memory comprises a three-dimensional memory.

9. The storage system of claim 1, wherein the storage system is embedded in a host.

10. The storage system of claim 1, wherein the storage system is removably connected to a host.

2. A storage system comprising:

a memory comprising a plurality of physical blocks of memory; and

a controller in communication with the memory, wherein the controller is configured to;

identify at least two physical blocks of memory that are designated as bad blocks because of at least one defective wordline;

identify which wordlines in the at least two physical blocks of memory are defective; and

create a logical block of memory from non-defective wordlines in the at least two physical blocks of memory, wherein some portions of the logical block are mapped to one of the at least two physical blocks of memory, and wherein other portions of the logical block are mapped to another one of the at least two physical blocks of memory;

wherein the controller is configured to identify the at least two physical blocks of memory by determining that a number of non-defective wordlines in the at least two physical blocks of memory sum up to at least a number of wordlines needed to create a logical block.

11. A method for bad block recycling, the method comprising:

determining a bit error rate for each of a plurality of bad blocks of memory in a storage system; and

writing data N number of limes, once in each of N number of bad blocks having a same bit error rate, wherein N>

1 and is based on the bit error rate and increases as the bit error rate increases.

12. The method of claim 11, wherein the memory comprises a three-dimensional memory.

13. The method of claim 11, wherein the storage system is embedded in a host.

14. The method of claim 11, wherein the storage system is removably connected to a host.

15. A storage system comprising:

a memory comprising a plurality of physical blocks of memory;

means for identifying at least two physical blocks of memory that are designated as bad blocks because of at least one defective wordline;

means for identifying which wordlines in the at least two physical blocks of memory are defective; and

means for creating a logical block of memory from non-defective wordlines in the at least two physical blocks of memory, wherein some portions of the logical block are mapped to one of the at least two physical blocks of memory, and wherein other portions of the logical block are mapped to another one of the at least two physical blocks of memory.

16. The storage system of claim 15 further comprising means for identifying the at least two physical blocks of memory by determining that a number of non-defective wordlines in the at least two physical blocks of memory sum up to at least a number of wordlines needed to create the logical block.

17. The storage system of claim 15 further comprising means for writing data redundantly in N number of bad blocks having a same bit error rate, wherein N is based on the bit error rate and increases as the bit error rate increases.

18. The storage system of claim 15, wherein the memory comprises a three-dimensional memory.

19. The storage system of claim 15, wherein the storage system is embedded in a host.

20. The storage system of claim 15, wherein the storage system is removably connected to a host.