Methods Of Forming An Array Comprising Pairs Of Vertically Opposed Capacitors And Arrays Comprising Pairs Of Vertically Opposed Capacitors

• US 20180315658A1
• Filed: 06/14/2018
• Published: 11/01/2018
• Est. Priority Date: 11/01/2016
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Ramaswamy, Durai Vishak Nirmal
• Granted Patent: US 10,903,122 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 28/55 with a dielectric comprising a perovskite structure material
• CPC Class Codes: H01L 28/60 Electrodes
• CPC Class Codes: H01L 28/90 having vertical extensions
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices
• CPC Class Codes: H10B 53/30 characterised by the memory core region

Abstract

A method of forming an array comprising pairs of vertically opposed capacitors comprises forming a conductive lining in individual capacitor openings in insulative-comprising material. An elevational mid-portion of individual of the conductive linings is removed to form an upper capacitor electrode lining and a lower capacitor electrode lining that are elevationally separate and spaced from one another in the individual capacitor openings. A capacitor insulator is formed laterally inward of the upper and lower capacitor electrode linings in the individual capacitor openings. Conductive material is formed laterally inward of the capacitor insulator in the individual capacitor openings and elevationally between the capacitor electrode linings. The conductive material is formed to comprise a shared capacitor electrode that is shared by vertically opposed capacitors in individual of the pairs of vertically opposed capacitors. Additional methods and structure independent of method are disclosed.

Claims

1-28. -28. (canceled)

29. A method of forming an array comprising upper capacitors that are above lower capacitors, the method comprising:

using one and only one photolithographic patterning step in collectively forming all radial outlines of both of;

a) all lower capacitor electrodes of individual of the lower capacitors; and

b) all upper capacitor electrodes of individual of the upper capacitors.

30. The method of claim 29 comprising forming all of the individual lower capacitor electrodes to be of a container shape and forming all of the individual upper capacitor electrodes to be of a container shape.

31. The method of claim 29 comprising forming the all of the individual lower capacitor electrodes to be of an upwardly-open container shape and forming all of the individual upper capacitor electrodes to be of a downwardly-open container shape.

32. The method of claim 31 comprising forming a shared capacitor electrode vertically between all of the individual lower capacitor electrodes and all of the individual upper capacitor electrodes after forming the individual upper and lower capacitor electrodes.

33. A method of forming an array comprising:

forming lower vertical transistors individually comprising a lower source/drain region, an upper source/drain region, and a channel region vertically there-between;

forming upper capacitors that are above lower capacitors, the lower capacitors being directly electrically coupled to individual of the upper source/drain regions of individual of the lower vertical transistors, the upper and lower capacitors sharing a capacitor electrode; and

forming upper vertical transistors individually comprising a lower source/drain region, an upper source/drain region, and a channel region vertically there-between, the upper capacitors being directly electrically coupled to individual of the lower source/drain regions of individual of the upper vertical transistors.

34. The method of claim 33 comprising forming the upper source/drain regions of the lower vertical transistors to comprising an uppermost conductive etch stop material, the forming of the lower capacitors comprising etching individual openings into insulative material, the etching being conducted to and selectively relative to the conductive etch stop material.

35. The method of claim 33 comprising forming the upper capacitors to individually comprise an upper capacitor electrode of a downwardly-open container shape.

36. The method of claim 33 comprising forming the lower capacitors to individually comprise a lower capacitor electrode of an upwardly-open container shape.

37. A method of forming an array comprising upper capacitors that are above lower capacitors, the method comprising:

forming a lower insulator material above a base substrate;

forming a sacrificial material above the lower insulator material;

forming an upper insulator material above the sacrificial material; and

forming upper capacitors that are above lower capacitors, individual of the upper capacitors comprising a non-shared capacitor electrode within the upper insulator material, individual of the lower capacitors comprising a non-shared capacitor electrode within the lower insulator material, the upper and lower capacitors comprising a shared capacitor electrode, the forming of the upper and lower capacitors comprising removing all of the sacrificial material prior to forming the shared capacitor electrode.

38. The method of claim 37 wherein the sacrificial material is not dielectric.

39. The method of claim 38 wherein the sacrificial material is predominately elemental-form silicon.

40. The method of claim 37 wherein the sacrificial material is dielectric.

41. The method of claim 37 comprising forming each of the lower insulator material, the sacrificial material, and the upper insulator material to have a planar top surface.

42. A method of forming an array comprising pairs of vertically opposed capacitors, comprising:

forming insulative-comprising material above a base substrate;

forming a conductive lining in individual capacitor openings in the insulative-comprising material;

removing a vertical mid-portion of individual of the conductive linings to form an upper capacitor electrode lining and a lower capacitor electrode lining that are vertically separate and vertically spaced from one another in the individual capacitor openings;

forming a capacitor insulator radially inside of the upper and lower capacitor electrode linings in the individual capacitor openings; and

forming conductive material radially inside of the capacitor insulator in the individual capacitor openings and vertically between the capacitor electrode linings to comprise a shared capacitor electrode that is shared by vertically opposed capacitors in individual of the pairs of vertically opposed capacitors.

43. The method of claim 42 comprising forming the shared capacitor electrode to also be shared by multiple of the pairs of vertically opposed capacitors.

44. The method of claim 42 wherein the conductive lining in the individual capacitor openings comprises a container shape comprising sidewalls and a bottom extending laterally to and between the sidewalls. The method of claim 42 comprising forming the conductive lining to be upwardly open.

46. The method of claim 42 comprising forming the conductive lining, the upper capacitor electrode lining, and the lower capacitor electrode lining to be totally encircling in the individual capacitor openings in horizontal cross-section.

47. The method of claim 42 comprising forming the upper capacitor electrode lining to comprise a downwardly-facing container shape comprising sidewalls and a top extending radially to and between the sidewalls.

48. The method of claim 47 wherein the capacitor insulator is vertically thicker between the top of the upper capacitor electrode lining and the shared capacitor electrode at its radial center than it is laterally thick between the sidewalls of the upper capacitor electrode lining and the shared capacitor electrode.

49. A method of forming an array comprising pairs of vertically opposed capacitors, comprising:

forming an upwardly-open conductive lining in individual capacitor openings, the capacitor openings extending vertically through upper insulative material that is formed above a base substrate, the capacitor openings extending vertically into lower insulative material, to capacitor openings extending vertically through sacrificial material that is elevationally between the upper and lower insulative materials and to a node location, individual of the conductive linings in the individual capacitor openings directly electrically coupling to individual of the node locations;

forming covering material over radially-inside sidewalls of the conductive linings in the individual capacitor openings, the covering material covering at least a majority of those radially-inside sidewalls;

after forming the covering material, removing both of the sacrificial material and a vertical mid-portion of the individual conductive linings that is vertically between the upper and lower insulative materials in the individual capacitor openings, the removing being conducted selectively relative to the covering material and the upper and lower insulative materials, the removing of the sacrificial material forming a void space vertically between the upper and lower insulative materials laterally between radially outside of the individual capacitor openings, an upper portion of the individual capacitor openings extending vertically down to the void space, a lower portion of the individual capacitor openings extending vertically up to the void space, the removing of the vertical mid-portion of the individual conductive linings that is vertically between the upper and lower insulative materials in the individual capacitor openings separating the individual conductive linings into an upper capacitor electrode lining and a lower capacitor electrode lining;

forming a capacitor insulator radially inside of the upper and lower capacitor electrode linings in the individual capacitor openings and against walls of the void space to less-than-fill the void space and less-than-fill remaining volume of the upper and lower portions of the individual capacitor openings; and

forming conductive material radially inside of the capacitor insulator in the individual capacitor openings and in the void space to comprise a shared capacitor electrode that is shared by vertically opposed capacitors in individual of the pairs of vertically opposed capacitors and is shared by multiple of the pairs of vertically opposed capacitors.

50. The method of claim 49 wherein the removing comprises removing at least a majority of the sacrificial material before removing the mid-portion of the individual conductive linings that is vertically between the upper and lower insulative materials in the individual capacitor openings.

51. The method of claim 49 wherein the removing comprises removing the mid-portion of the individual conductive linings that is vertically between the upper and lower insulative materials in the individual capacitor openings before removing at least a majority of the sacrificial material.