HIGH PERFORMANCE INTEGRATED RF PASSIVES USING DUAL LITHOGRAPHY PROCESS

• US 20180315690A1
• Filed: 12/21/2015
• Published: 11/01/2018
• Est. Priority Date: 12/21/2015
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: ELSHERBINI, Adel A., MANUSHAROW, Mathew J., BHARATH, Krishna, LAMBERT, William J., SANKMAN, Robert L., ALEKSOV, Aleksandar, RAWLINGS, Brandon M., EID, Feras, SOTO GONZALEZ, Javier, JIAO, Meizi, NAD, Suddhasattwa, KAMGAING, Telesphor
• Granted Patent: US 11,227,825 B2
• Time in Patent Office: Days
• CPC Class Codes: H01F 17/0006 Printed inductances printed coils for dynamo-electric machines H02K3/26; printed circuits H05K
• CPC Class Codes: H01F 2027/2809 on stacked layers
• CPC Class Codes: H01F 27/2804 Printed windings
• CPC Class Codes: H01F 27/40 Structural association with built-in electric component, e.g. fuse
• CPC Class Codes: H01F 41/041 Printed circuit coils apparatus or processes for manufacturing printed circuits in general H05K3/00
• CPC Class Codes: H01G 4/33 Thin- or thick-film capacitors thin- or thick-film circuits H01L27/00; capacitors without a potential-jump or surface barrier specially adapted for integrated circuits, details thereof, multistep manufacturing processes therefor H01L28/40
• CPC Class Codes: H01L 21/4857 Multilayer substrates multilayer metallisation on monolayer substrate H01L21/4846
• CPC Class Codes: H01L 21/486 Via connections through the substrate with or without pins
• CPC Class Codes: H01L 2223/6661 for passive devices passive components per se H01L28/00
• CPC Class Codes: H01L 23/49822 Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/49838 Geometry or layout
• CPC Class Codes: H01L 23/66 High-frequency adaptations
• CPC Class Codes: H01L 28/00 Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor testing or measuring during manufacture H01L22/00; integration methods H01L21/70; integrated circuits H01L27/00; two-terminal components with a potential-jump or surface barrier H01L29/00; resistors in general H01C; inductors in general H01F; capacitors in general H01G
• CPC Class Codes: H01L 28/10 Inductors
• CPC Class Codes: H01L 28/60 Electrodes

Abstract

Embodiments of the invention include an electrical package and methods of forming the package. In one embodiment, a transformer may be formed in the electrical package. The transformer may include a first conductive loop that is formed over a first dielectric layer. A thin dielectric spacer material may be used to separate the first conductive loop from a second conductive loop that is formed in the package. Additional embodiments of the invention include forming a capacitor formed in the electrical package. For example, the capacitor may include a first capacitor plate that is formed over a first dielectric layer. A thin dielectric spacer material may be used to separate the first capacitor plate form a second capacitor plate that is formed in the package. The thin dielectric spacer material in the transformer and capacitor allow for increased coupling factors and capacitance density in electrical components.

Claims

1. A transformer formed in an electrical package comprising:

a first dielectric layer;

a first conductive loop formed over a surface of the first dielectric layer;

a dielectric spacer formed over the first conductive loop; and

a second conductive loop separated from the first conductive loop by the dielectric spacer layer.

2. The transformer of claim 1, wherein the second conductive loop is formed above the first conductive loop.

3. The transformer of claim 2, wherein the first conductive loop and the second conductive loop are formed in a single routing layer of the electrical package.

4. The transformer of claim 2, wherein the dielectric spacer layer is former only over a top surface of the first conductive loop.

5. The transformer of claim 1, wherein the second conductive loop is formed over the first dielectric layer, and wherein a sidewall surface of the first conductive loop is separated from a sidewall surface of the second conductive loop by the dielectric spacer.

6. The transformer of claim 5, wherein the dielectric spacer includes a cap layer formed over a top surface of the first conductive loop and a sidewall spacer formed over the sidewalls of the first conductive loop.

7. The transformer of claim 6, wherein the cap layer is a different material than the sidewall spacer.

8. The transformer of claim 5, wherein the second conductive loop is formed inside a perimeter of the first conductive loop.

9. The transformer of claim 1, wherein the dielectric spacer layer has a thickness that is less than 20 μ

m.

10. The transformer of claim 9, wherein the dielectric spacer layer has a thickness that is less than 5 μ

m.

11. A method of forming a transformer in an electrical package, comprising:

forming a first conductive loop over a first dielectric layer;

forming a dielectric spacer layer over the first conductive loop; and

forming a second conductive loop in direct contact with the dielectric spacer layer, wherein the first conductive loop is spaced apart from the second conductive loop by only the dielectric spacer layer.

12. The method of claim 11, wherein the second conductive loop is formed over a top surface of the first conductive loop.

13. The method of claim 12, wherein forming the second conductive loop comprises:

forming a seed layer over the dielectric spacer layer;

depositing and patterning a photoresist material to form openings above the first conductive loop; and

plating a conductive material in the openings.

14. The method of claim 11, wherein the second conductive loop is formed side-by-side with the first conductive loop.

15. The method of claim 14, wherein forming the dielectric spacer layer comprises:

forming a cap layer over a top surface of the first conductive loop;

forming a conformal spacer layer over the exposed surfaces; and

etching the conformal spacer layer with an anisotropic etching process to remove the conformal spacer layer from horizontal surfaces, wherein a sidewall spacer remains along sidewalls of the first conductive loop.

16. A capacitor formed in an electrical package comprising:

a first dielectric layer;

a first capacitor plate formed over a surface of the first dielectric layer;

a dielectric spacer formed over a surface of the first capacitor plate; and

a second capacitor plate separated from the first capacitor plate by the dielectric spacer layer.

17. The capacitor of claim 16, wherein the first and second capacitor plates are formed in a single routing layer of the package.

18. The capacitor of claim 17, wherein the dielectric spacer is less than 10 μ

m thick.

19. The capacitor of claim 16, wherein the first and second capacitor plates include interdigitated square meander extensions.

20. The capacitor plate of claim 19, wherein the extensions are formed in three-dimensions.

21. A method for forming a capacitor in an electrical package, comprising:

forming a first capacitor plate over a first dielectric layer;

forming a dielectric spacer layer over the first capacitor plate; and

forming a second capacitor plate in direct by with the dielectric spacer layer, wherein the first capacitor plate is spaced apart from the second capacitor plate by only the dielectric spacer layer.

22. The method of claim 21, wherein forming the first capacitor plate comprises:

forming a first seed layer over the first dielectric layer;

depositing a photoresist material over the first seed layer;

patterning the photoresist material to form one or more openings; and

depositing a conductive material into the openings.

23. The method of claim 21, wherein the dielectric spacer layer is formed with a screen printing process, a chemical vapor depositions process, a lamination process, or a photolithographic patterning of a photodefinable dielectric layer.

24. The method of claim 21, wherein forming the second capacitor plate comprises:

forming a second seed layer over a surface of the dielectric spacer layer; and

growing the second capacitor plate form the second seed layer with an electroplating process.

25. The method of claim 24, wherein the second capacitor plate is formed concurrently with the formation of one or more vias.