FINFET DEVICE WITH NON-RECESSED STI

• US 20180315839A1
• Filed: 03/12/2018
• Published: 11/01/2018
• Est. Priority Date: 04/26/2017
• Status: Active Grant

• Current Assignee: Semiconductor Manufacturing International Corporation
• Original Assignee: Semiconductor Manufacturing International Corporation
• Inventors: ZHOU, FEI
• Granted Patent: US 10,644,135 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A method for manufacturing a semiconductor device includes providing a semiconductor structure having a substrate and a semiconductor fin on the substrate, forming a dummy gate structure on the semiconductor fin, forming a first dielectric layer on the semiconductor structure exposing an upper surface of the dummy gate structure, removing the dummy gate structure and a portion of the semiconductor fin below the dummy gate structure to form a trench that divides the semiconductor fin into a first portion and a second portion spaced apart from each other, and forming a second dielectric layer on the semiconductor structure filling the trench. The method provides a semiconductor device having a non-recessed trench isolation structure.

Claims

1. A method for manufacturing a semiconductor device, comprising:

providing a semiconductor structure including a substrate and a semiconductor fin on the substrate;

forming a dummy gate structure on the semiconductor fin;

forming a first dielectric layer on the semiconductor structure exposing an upper surface of the dummy gate structure;

removing the dummy gate structure and a portion of the semiconductor fin below the dummy gate structure to form a trench that divides the semiconductor fin into a first portion and a second portion spaced apart from each other; and

forming a second dielectric layer on the semiconductor structure filling the trench.

2. The method of claim 1, further comprising:

forming a first initial gate structure and a second initial gate structure on the semiconductor fin on opposite sides of the dummy gate structure, the first and second initial gate structures being spaced apart from the dummy gate structure.

3. The method of claim 2, further comprising:

forming a first hardmask layer on the dummy gate structure and the first and second initial gate structures;

forming spacers on sidewalls of the dummy gate structure and on sidewalls of the first and second initial gate structures.

4. The method of claim 3, further comprising:

forming a first electrode and a second electrode on opposite sides of the first initial gate structure and a third electrode and a fourth electrode on opposite sides of the second initial gate structure;

wherein the second electrode is disposed between the first initial gate structure and the dummy gate structure, and the third electrode is disposed between the second initial gate structure and the dummy gate structure.

5. The method of claim 4, further comprising:

forming a first contact, a second contact, a third contact, and a fourth contact extending through the first dielectric layer and the second dielectric layer to connect to the first electrode, the second electrode, the third electrode, and the fourth electrode, respectively.

6. The method of claim 5, further comprising, after forming the dummy gate structure, the first initial gate structure and the second initial gate structure:

forming a first dielectric layer on the semiconductor structure; and

planarizing the first dielectric layer to expose an upper surface of the dummy gate structure, an upper surface of the first initial gate structure, and an upper surface of the second initial gate structure.

7. The method of claim 6, wherein:

the dummy gate structure comprises a dummy gate insulator layer on the semiconductor fin and a dummy gate on the dummy gate insulator layer;

the first initial gate structure comprises a first initial gate insulator layer on the semiconductor fin and a first initial gate on the first initial gate insulator layer;

the second initial gate structure comprises a second initial gate insulator layer on the semiconductor fin and a second initial gate on the second initial gate insulator layer;

wherein the upper surface of the dummy gate structure is an upper surface of the dummy gate, the upper surface of the first initial gate structure is an upper surface of the first initial gate, and the upper surface of the second initial gate structure is an upper surface of the second initial gate.

8. The method of claim 7, further comprising, prior to forming the trench:

removing the first initial gate structure and the second initial gate structure to form a first recess in a location of the removed first initial gate structure and a second recess in a location of the removed second initial gate structure;

forming a first gate structure in the first recess and a second gate structure in the second recess;

removing a top portion of the first gate structure to form a third recess and a top portion of the second gate structure to form a fourth recess, the third recess having a depth less than a depth of the first recess, and the fourth recess having a depth less than a depth of the second recess; and

forming a second hardmask layer on an upper surface of the first gate structure and an upper surface of the second gate structure.

9. The method of claim 8, wherein the first gate structure is disposed on the first portion, the first electrode and the second electrode being disposed in the first portion, the second gate structure is disposed on the second portion, the third electrode and the fourth electrode being disposed in the second portion.

10. The method of claim 8, wherein forming the first recess and the second recess comprises:

forming a patterned mask layer on the first dielectric layer covering the dummy gate and exposing an upper surface of the first initial gate and an upper surface of the second initial gate;

removing the first initial gate and the second initial gate using the patterned mask layer as a mask;

removing the patterned mask layer;

removing the first initial gate insulator layer and the second initial gate insulator layer to form the first recess and the second recess.

11. The method of claim 8, wherein forming the second hardmask layer comprises:

forming the second hardmask layer filling the third recess and the fourth recess;

planarizing the second hardmask layer to expose an upper surface of the dummy gate, wherein a remaining portion of the second hardmask layer comprises a first hardmask portion disposed on the first gate structure and a second hardmask portion disposed on the second gate structure.

12. The method of claim 1, wherein the trench comprises a depth in a range between 2000 angstroms and 4000 angstroms, and a first trench portion between the first portion and the second portion and a second trench portion above the first trench portion;

wherein the first trench portion has a depth in a range between 1000 angstroms and 2000 angstroms, and the second trench portion has a depth in a range between 1000 angstroms and 2000 angstroms.

13. The method of claim 1, further comprising:

forming a trench isolation portion on the substrate and surrounding the semiconductor fin, the trench isolation portion having a bottom substantially flush with a bottom of the trench.

14. A semiconductor device, comprising:

a substrate;

a semiconductor fin on the substrate;

a first dielectric layer on the semiconductor fin;

a trench on the substrate and in the semiconductor fin and the first dielectric layer, the trench dividing the semiconductor fin into a first portion and a second portion that are spaced apart from each other; and

a second dielectric layer on the first dielectric layer and filling the trench.

15. The semiconductor device of claim 14, further comprising:

a first gate structure and a second gate structure on opposite sides of the trench, the first gate structure being on the first portion and the second gate structure being on the second portion.

16. The semiconductor device of claim 15, further comprising:

a hardmask layer on an upper surface of the first gate structure and on an upper surface of the second gate structure; and

a spacer on sidewalls of the first gate structure and the second gate structure.

17. The semiconductor device of claim 15, further comprising:

a first electrode and a second electrode on opposite sides of the first gate structure; and

a third electrode and a fourth electrode on opposite sides of the second gate structure.

18. The semiconductor device of claim 17, further comprising:

a first contact, a second contact, a third contact, and a fourth contact each extending through the first dielectric layer and the second dielectric layer and connecting to a first electrode, a second electrode, a third electrode, and a fourth electrode, respectively.

19. The semiconductor device of claim 14, wherein the trench comprises a depth in a range between 2000 angstroms and 4000 angstroms, and a first trench portion between the first portion and the second portion and a second trench portion above the first trench portion,

the first trench portion having a depth in a range between 1000 angstroms and 2000 angstroms, and the second trench portion having a depth in a range between 1000 angstroms and 2000 angstroms.

20. The semiconductor device of claim 14, further comprising:

a trench isolation portion on the substrate and surrounding the semiconductor fin, the trench isolation portion having a bottom that is substantially flush with a bottom of the trench.