Transistor Switch

• US 20180316343A1
• Filed: 04/28/2017
• Published: 11/01/2018
• Est. Priority Date: 04/28/2017
• Status: Abandoned Application

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Goktepeli, Sinan
• Application Number:
  US15/582,080
• Publication Number:
  US 20180316343A1
• Time in Patent Office: Days
• CPC Class Codes: H03K 17/165 by feedback from the output circuit to the control circuit
• CPC Class Codes: H03K 17/168 in composite switches
• CPC Class Codes: H03K 17/687 the devices being field-effect transistors
• CPC Class Codes: H03K 17/693 Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors logic circuits H03K19/00; code converters H03M5/00, H03M7/00
• CPC Class Codes: H03K 17/74 by the use, as active elements, of diodes by the use of more than one type of semiconductor device H03K17/567; by the use of tunnel diodes H03K17/58; by the use of negative resistance diodes H03K17/70
• CPC Class Codes: H03K 2017/066 Maximizing the OFF-resistance instead of minimizing the ON-resistance
• CPC Class Codes: H03K 2217/0018 Special modifications or use of the back gate voltage of a FET
• CPC Class Codes: H03K 2217/0054 Gating switches, e.g. pass gates
• CPC Class Codes: H04B 1/44 Transmit/receive switching

Abstract

Various aspects of this disclosure describe configuring and operating a transistor switch. Examples include a biasing circuit that contains a pair of diodes and a pair of resistors. The resistors may be placed in parallel by forward-biasing the pair of diodes. When the transistor is disabled (e.g., switch is open), gate-induced-drain-leakage (GIDL) current from the transistor, when flowing, may be split between each of the resistors to inhibit a voltage drop on the gate of the transistor, which may reduce harmonic distortion and/or increase the breakdown voltage of the transistor. The resistor values can be selected to ensure that the gate voltage of the transistor stays approximately equal to a negative bias voltage.

Claims

1. A switch comprising:

a transistor;

a first diode having an anode connected to a body of the transistor and a cathode connected to a gate of the transistor;

a first resistor connected to the gate of the transistor and a voltage; and

a second resistor connected to the body of the transistor and an anode of a second diode, the second diode having a cathode connected to the voltage.

2. The switch as recited in claim 1, wherein the second resistor has a resistance value less than a resistance value of the first resistor.

3. The switch as recited in claim 1, wherein the second resistor has a resistance value that is nominally half a resistance value of the first resistor.

4. The switch as recited in claim 1, wherein the switch is configured such that gate-induced-drain-leakage (GIDL) current, when flowing, flows from the body of the transistor through the first resistor and the second resistor, and more GIDL current flows through the second resistor than flows through the first resistor.

5. The switch as recited in claim 1, wherein the switch is configured such that gate-induced-drain-leakage (GIDL) current, when flowing, flows from the body of the transistor through the first resistor and the second resistor, and GIDL current that flows through the second resistor causes a higher breakdown voltage of the transistor compared to when no GIDL flows through the second resistor.

6. The switch as recited in claim 1, wherein the switch is configured such that gate-induced-drain-leakage (GIDL) current, when flowing, flows from the body of the transistor through the first resistor and the second resistor, and GIDL current that flows through the second resistor causes a lower harmonic distortion of the transistor compared to when no GIDL flows through the second resistor.

7. The switch as recited in claim 1, wherein the second resistor causes a voltage on the gate of the transistor to become more negative when the transistor is in an off state compared to when the second resistor is disconnected from the switch.

8. The switch as recited in claim 1, wherein when the transistor is in an off state, the first resistor and the second resistor are in parallel.

9. The switch as recited in claim 1, wherein the transistor, the first diode, the second diode, the first resistor, and the second resistor are implemented in a System-on-Chip (SoC).

10. The switch as recited in claim 1, wherein the switch is coupled to a source of a radio frequency (RF) signal.

11. The switch as recited in claim 1, wherein the switch is coupled to an output of a power amplifier.

12. The switch as recited in claim 1, wherein the switch is coupled to an antenna and is configured to switch between transmit and receive signals.

13. A method of operating a switch, the method comprising:

applying a first voltage to a gate of a transistor through a first resistor to disable the transistor in an off state;

placing a second resistor in parallel with the first resistor responsive to the applying the first voltage;

causing gate-induced-drain-leakage (GIDL) current to flow through the second resistor;

applying a second voltage to the gate of the transistor to enable the transistor in an on state; and

removing the second resistor from being in parallel with the first resistor responsive to the applying the second voltage.

14. The method as recited in claim 13, wherein the first voltage is negative and the second voltage is positive.

15. The method as recited in claim 13, wherein the second resistor has a resistance value less than a resistance value of the first resistor.

16. The method as recited in claim 13, wherein less GIDL current flows through the first resistor than the second resistor.

17. The method as recited in claim 13, wherein the placing the second resistor comprises forward-biasing a pair of diodes and the removing the second resistor comprises reverse-biasing the pair of diodes.

18. The method as recited in claim 17, wherein one of the diodes is configured with an anode connected to a body of the transistor and a cathode connected to the gate of the transistor, and the other of the diodes is configured with an anode connected to the second resistor and a cathode connected to a voltage source used for the applying the first voltage.

19. The method as recited in claim 13, wherein the causing the GIDL current to flow through the second resistor causes the first voltage to become more negative compared to when no current flows through the second resistor.

20. A device comprising:

means for applying a first voltage to a gate of a transistor through a first resistor to disable the transistor in an off state;

means for placing a second resistor in parallel with the first resistor responsive to the applying the first voltage; and

means for causing gate-induced-drain-leakage (GIDL) current to flow through the second resistor.

21. The device as recited in claim 20, wherein the second resistor has a resistance value less than a resistance value of the first resistor.

22. The device as recited in claim 20, wherein the means for causing the GIDL current to flow comprises means for flowing less GIDL current through the first resistor than the second resistor.

23. The device as recited in claim 20, wherein the means for placing the second resistor comprises means for forward-biasing a pair of diodes.

24. The device as recited in claim 20, further comprising:

means for applying a second voltage to the gate of the transistor to enable the transistor in an on state; and

means for removing the second resistor from being in parallel with the first resistor responsive to the applying the second voltage.

25. The device as recited in claim 24, wherein the means for removing the second resistor comprises means for reverse-biasing a pair of diodes.

26. A system comprising:

a transistor;

a first resistor having a first terminal connected to a gate of the transistor and a second terminal coupled to a voltage input;

a second resistor having a first terminal connected to a body of the transistor and a second terminal coupled to the voltage input; and

a pair of diodes configured to selectively place the first resistor and the second resistor in parallel.

27. The system as recited in claim 26, wherein the pair of diodes are configured to place the first resistor and the second resistor in parallel when the pair of diodes are forward-biased.

28. The system as recited in claim 26, wherein the second resistor has a resistance value less than a resistance value of the first resistor.

29. The system as recited in claim 26, wherein when the transistor is disabled in an off state, gate-induced-drain-leakage (GIDL) current, when flowing, flows from the body of the transistor through the first resistor and the second resistor, and more GIDL current flows through the second resistor than flows through the first resistor.

30. The system as recited in claim 26, wherein the transistor, the first resistor, the second resistor, and the pair of diodes are fabricated in a same process type.