TRENCH MOSFET DEVICE AND THE PREPARATION METHOD THEREOF

• US 20180323155A1
• Filed: 06/21/2018
• Published: 11/08/2018
• Est. Priority Date: 06/30/2016
• Status: Active Grant

• Current Assignee: Alpha & Omega Semiconductor, Ltd.
• Original Assignee: Alpha & Omega Semiconductor, Ltd.
• Inventors: Wang, Xiaobin, Bobde, Madhur, Thorup, Paul
• Granted Patent: US 10,665,551 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/265 producing ion implantation
• CPC Class Codes: H01L 23/562 Protection against mechanical damage H01L23/02, H01L23/28 take precedence
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A trench-type metal-oxide-semiconductor field-effect transistor (MOSFET) device and a fabrication method are disclosed. A semiconductor substrate of a first conductivity type is provided. A plurality of first trenches arranged side by side in a first stripe layout extending along a first direction in a first preset area of the semiconductor substrate are formed. A plurality of second trenches arranged side by side in a second stripe layout extending along a second direction perpendicular to the first direction in a second preset area of the semiconductor substrate are formed. The plurality of first trenches and the plurality of second trenches are filled with a conductive material so as to form a plurality of control gates.

Claims

1. A method for fabricating a trench metal-oxide-semiconductor field-effect transistor (MOSFET) device, the method comprising the steps of:

providing a semiconductor substrate of a first conductivity type;

forming a plurality of first trenches arranged side by side in a first stripe layout extending along a first direction in a first preset area of the semiconductor substrate;

forming a plurality of second trenches arranged side by side in a second stripe layout extending along a second direction perpendicular to the first direction in a second preset area of the semiconductor substrate;

filling the plurality of first trenches and the plurality of second trenches with a conductive material so as to form a plurality of control gates;

implanting dopant of a second conductivity type on a top portion of the semiconductor substrate to form a body region; and

implanting dopant of the first conductivity type on a top portion of the body region to form a source region.

2. The method of claim 1, wherein the step of forming the plurality of first trenches and the step of forming the plurality of second trenches comprising:

applying a mask layer covering a top surface of the semiconductor substrate;

forming openings in the mask layer; and

etching the semiconductor substrate through the openings in the mask layer so as to form the plurality of first trenches and the plurality of second trenches.

3. The method of claim 1 further comprising:

before the step of filling the plurality of first trenches and the plurality of second trenches with the conductive material,

covering a first insulation layer over a bottom surface and sidewalls of each of the plurality of first trenches and the plurality of second trenches.

4. The method of claim 3, wherein the step of filling the plurality of first trenches and the plurality of second trenches with the conductive material so as to form the plurality of control gates comprises:

depositing the conductive material on the semiconductor substrate so the plurality of first trenches and the plurality of second trenches are filled with the conductive material; and

etching away an excessive portion of the conductive material so that the plurality of control gates are formed from a remaining portion of the conductive material in the plurality of first trenches and the plurality of second trenches.

5. The method of claim 4 further comprising:

after the step of implanting dopant of the first conductivity type on the top portion of the body region to form the source region,

forming a passivation layer on the plurality of control gate in the plurality of first trenches and the plurality of second trenches and on the semiconductor substrate;

etching the passivation layer to form a plurality of stripe contact trenches penetrating the passivation layer, the source region and an upper portion of the body region; and

filling the plurality of stripe contact trenches with another metal material;

wherein the stripe contact trenches are formed between adjacent first trenches of the plurality of first trenches and between adjacent second trenches of the plurality of second trenches.

6. The method of claim 3, wherein the step of filling the plurality of first trenches and the plurality of second trenches with the conductive material so as to form the plurality of control gates comprises:

depositing the conductive material on the semiconductor substrate so that the plurality of first trenches and the plurality of second trenches are filled with the conductive material;

etching away an excessive portion of the conductive material so that a plurality of shield gates are formed from a remaining portion of the conductive material in lower portions of the plurality of first trenches and the plurality of second trenches;

depositing an insulation material on the semiconductor substrate so that the plurality of first trenches and the plurality of second trenches are filled with the insulation material;

etching away an excessive portion of the insulation material so as to form an insulation interlayer on the plurality of shield gates;

growing another insulation layer on a top surface of the semiconductor substrate and on exposed sidewalls at top portions of the plurality of first trenches and the plurality of second trenches;

depositing the conductive material on the semiconductor substrate so that the plurality of first trenches and the plurality of second trenches are filled with the conductive material; and

etching away another excessive portion of the conductive material so that the plurality of control gates are formed from another remaining portion of the conductive material in the plurality of first trenches and the plurality of second trenches.

7. The method of claim 6 further comprising:

after the step of implanting dopant of the first conductivity type on the top portion of the body region to form the source region,

forming a passivation layer on the plurality of control gate in the plurality of first trenches and the plurality of second trenches and on the semiconductor substrate;

etching the passivation layer to form a plurality of stripe contact trenches penetrating the passivation layer, the source region and an upper portion of the body region; and

filling the plurality of stripe contact trenches with another metal material;

wherein the stripe contact trenches are formed between adjacent first trenches of the plurality of first trenches and between adjacent second trenches of the plurality of second trenches.

8. The method of claim 1, wherein an end of at least one selected first trench of the plurality of first trenches is connected to a selected second trench of the plurality of second trenches.