SOLID-STATE IMAGING DEVICE AND IMAGING APPARATUS

• US 20180323231A1
• Filed: 07/16/2018
• Published: 11/08/2018
• Est. Priority Date: 01/19/2016
• Status: Active Grant

• Current Assignee: Olympus Corporation
• Original Assignee: Olympus Corporation
• Inventors: Saito, Haruhisa
• Granted Patent: US 10,644,059 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/522 including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• CPC Class Codes: H01L 25/065 the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 25/07 the devices being of a type provided for in group H01L29/00
• CPC Class Codes: H01L 25/18 the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 27/14 including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation radiation-sensitive components structurally associated with one or more electric light sources only H01L31/14; couplings of light guides with optoelectronic elements G02B6/42
• CPC Class Codes: H01L 27/146 Imager structures
• CPC Class Codes: H01L 27/14612 involving a transistor
• CPC Class Codes: H01L 27/14621 Colour filter arrangements
• CPC Class Codes: H01L 27/14627 Microlenses
• CPC Class Codes: H01L 27/14634 Assemblies, i.e. Hybrid structures
• CPC Class Codes: H01L 27/14636 Interconnect structures
• CPC Class Codes: H01L 27/1464 Back illuminated imager structures
• CPC Class Codes: H01L 27/14645 Colour imagers
• CPC Class Codes: H01L 27/1469 Assemblies, i.e. hybrid integration
• CPC Class Codes: H04N 25/70 SSIS architectures; Circuits associated therewith
• CPC Class Codes: H04N 25/75 Circuitry for providing, modifying or processing image signals from the pixel array

Abstract

A solid-state imaging device has a first substrate, a second substrate, and a third substrate. The first substrate has a plurality of first photoelectric conversion elements. The second substrate has a plurality of first through electrodes. The plurality of first photoelectric conversion elements are disposed in a pixel area. The plurality of first through electrodes are disposed only in a second area around a first area corresponding to the pixel area.

Claims

1. A solid-state imaging device comprising:

a first substrate having a first principal surface, a second principal surface, and a plurality of first photoelectric conversion elements, the first principal surface and the second principal surface facing in opposite directions, the plurality of first photoelectric conversion elements being disposed in a matrix form;

a second substrate having a third principal surface, a fourth principal surface, one or more first layers, and a plurality of first through electrodes, the third principal surface and the fourth principal surface facing in opposite directions, the third principal surface facing the second principal surface, the plurality of first through electrodes penetrating at least one of the first layers; and

a third substrate having a fifth principal surface and a sixth principal surface, the fifth principal surface and the sixth principal surface facing in opposite directions, the fifth principal surface facing the fourth principal surface,

wherein the plurality of first photoelectric conversion elements are disposed in a pixel area,

the plurality of first through electrodes are disposed only in a second area around a first area corresponding to the pixel area,

the first substrate and the second substrate are electrically connected to each other,

the second substrate comprises;

a first memory circuit disposed in the first area and configured to temporarily store signals output from the plurality of first photoelectric conversion elements;

a processing circuit disposed in the first area and configured to process the signals stored in the first memory circuit; and

a scanning circuit disposed in the second area and configured to control the plurality of first photoelectric conversion elements, the first memory circuit, and the processing circuit, and

the third substrate comprises;

a second memory circuit connected to the scanning circuit by the plurality of first through electrodes and configured to store the signals processed by the processing circuit.

2. The solid-state imaging device according to claim 1, further comprising:

a plurality of microbumps disposed between the second principal surface and the third principal surface, and

wherein each microbump included in the plurality of microbumps is disposed for each first photoelectric conversion element included in the plurality of first photoelectric conversion elements and electrically connects the first photoelectric conversion element and the first memory circuit to each other.

3. The solid-state imaging device according to claim 1, wherein the second substrate includes a plurality of processing circuits including the processing circuit,

each processing circuit included in the plurality of processing circuits is disposed for each column in an arrangement of the plurality of first photoelectric conversion elements, and

each processing circuit included in the plurality of processing circuits processes the signals output from the first photoelectric conversion element corresponding to the column and stored in the first memory circuit.

4. The solid-state imaging device according to claim 1, further comprising:

a first connection layer disposed between the first substrate and the second substrate and connecting the first substrate and the second substrate to each other,

wherein a plurality of microbumps are disposed in the first connection layer.

5. The solid-state imaging device according to claim 1, further comprising:

a second connection layer that is disposed between the second substrate and the third substrate and connects the second substrate and the third substrate to each other.

6. The solid-state imaging device according to claim 1, wherein the second substrate further includes at least one of a reading circuit and a plurality of second photoelectric conversion elements,

the reading circuit is configured to read the signals from the plurality of first photoelectric conversion elements, and

at least one of the reading circuit and the plurality of second photoelectric conversion elements is disposed in the first area.

7. The solid-state imaging device according to claim 1, wherein the third substrate further includes one or more second layers and a plurality of second through electrodes, and

the plurality of second through electrodes penetrate at least one of the second layers.

8. An imaging apparatus comprising the solid-state imaging device according to claim 1.