FIN-TYPE FIELD EFFECT TRANSISTOR AND METHOD OF FORMING THE SAME

• US 20180323256A1
• Filed: 07/19/2018
• Published: 11/08/2018
• Est. Priority Date: 10/02/2015
• Status: Active Grant

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation
• Inventors: Chiang, Huai-Tzu, Lin, Sheng-Hao, Lee, Hao-Ming, Yang, Yu-Ru, Huang, Shih-Hsien, Chen, Chien-Hung, Wu, Chun-Yuan, Tsai, Cheng-Tzung
• Granted Patent: US 10,439,023 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/2253 by ion implantation
• CPC Class Codes: H01L 21/76802 by forming openings in dielectrics
• CPC Class Codes: H01L 21/76871 Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
• CPC Class Codes: H01L 29/0615 by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] LDD or drain offset regions H01L29/7833
• CPC Class Codes: H01L 29/1033 with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with channel and gate aligned in the lengthwise direction H01L29/42376; with buried channel H01L29/7838
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

Provided is a FinFET including a substrate, at least one fin and at least one gate. A portion of the at least one fin is embedded in the substrate. The at least one fin includes, from bottom to top, a seed layer, a stress relaxation layer and a channel layer. The at least one gate is across the at least one fin. A method of forming a FinFET is further provided.

Claims

1. A method of forming a FinFET, comprising:

providing a substrate, wherein the substrate has an insulating layer formed thereon, the insulating layer has at least one trench formed therein, and the at least one trench extends to a portion of the substrate;

sequentially forming a seed layer, a stress relaxation layer and a channel layer in the at least one trench;

removing a portion of the insulating layer, so as to expose a portion of the channel layer; and

forming at least one gate across the channel layer.

2. The method of claim 1, further comprising forming an anti-punch through layer between the stress relaxation layer and the channel layer.

3. The method of claim 2, wherein a germanium concentration of the channel layer is substantially equal to a germanium concentration of the anti-punch through layer, the germanium concentration of the anti-punch through layer is greater than a germanium concentration of the stress relaxation layer, and the germanium concentration of the stress relaxation layer is greater than a germanium concentration of the seed layer.

4. The method of claim 2, wherein the stress relaxation layer has a graded stress distribution, and a germanium concentration of the stress relaxation layer is gradually increased from the seed layer towards the anti-punch through layer.

5. The method of claim 2, wherein a method of forming each of the seed layer, the stress relaxation layer, the anti-punch through layer and the channel layer comprises performing an epitaxial growth process.

6. The method of claim 2, wherein a dopant concentration of the anti-punch through layer is greater than a dopant concentration of the stress relaxation layer or the channel layer.

7. The method of claim 6, wherein a dopant of the anti-punch through layer comprises arsenic, phosphorus or boron.

8. The method of claim 2, wherein a surface of the remaining insulating layer is higher than an interface between the anti-punch through layer and the channel layer after the step of removing the portion of the insulating layer.

9. The method of claim 1, wherein a method of forming the at least one trench comprises:

providing the substrate with at least one dummy fin, wherein the insulating layer surrounds the at least one dummy fin; and

performing an etching process, so as to remove the at least one dummy fin and a portion of the substrate.

10. The method of claim 1, wherein a germanium concentration of the channel layer ranges from about 20% to 100%.

11. The method of claim 1, wherein the substrate and the seed layer have substantially the same lattice constant, and the anti-punch through layer and the channel layer have substantially the same lattice constant.

12. The method of claim 1, wherein the stress relaxation layer comprises germanium, the channel layer comprises a semiconductor material, the stress relaxation layer and the seed layer comprise different materials, and the seed layer has a tapered v-shaped tip at a bottom end thereof.