POWER DEVICE WITH HIGH ASPECT RATIO TRENCH CONTACTS AND SUBMICRON PITCHES BETWEEN TRENCHES

• US 20180323282A1
• Filed: 06/27/2018
• Published: 11/08/2018
• Est. Priority Date: 01/23/2015
• Status: Active Grant

• Current Assignee: Alpha & Omega Semiconductor, Inc. (Alpha & Omega Semiconductor, Ltd.)
• Original Assignee: Alpha & Omega Semiconductor, Inc. (Alpha & Omega Semiconductor, Ltd.)
• Inventors: Li, Wenjun, Thorup, Paul, Chang, Hong, Lee, Yeeheng, Xiang, Yang, Dun, Jowei, Xue, Hongyong, Gu, Yiming
• Granted Patent: US 10,424,654 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/2658 of a molecular ion, e.g. decaborane
• CPC Class Codes: H01L 21/28035 the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities H01L21/28105 takes precedence
• CPC Class Codes: H01L 29/0615 by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] LDD or drain offset regions H01L29/7833
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/66719 With a step of forming an insulating sidewall spacer
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

This invention discloses a semiconductor power device disposed in a semiconductor substrate including an active cell areas and a termination area. The semiconductor power device further comprises a plurality of gate trenches formed at a top portion of the semiconductor substrate in the active cell area wherein each of the gate trenches is partially filled with a conductive gate material with a top portion of the trenches filled by a high density plasma (HDP) insulation layer. The semiconductor power device further comprises mesa areas of the semiconductor substrate disposed between the gate trenches wherein the mesa areas are recessed and having a top mesa surface disposed vertically below a top surface of the HDP insulation layer wherein the HDP insulation layer covering over the conductive gate material constituting a stick-out boundary-defining layer surrounding the recessed mesa areas in the active cell areas between the gate trenches.

Claims

1. A semiconductor power device disposed in a semiconductor substrate including an active cell areas and a termination area wherein the semiconductor power device further comprising:

a plurality of gate trenches formed at a top portion of the semiconductor substrate in the active cell area wherein each of the gate trenches is partially filled with a conductive gate material with a top portion of the trenches covered by a high density plasma (HDP) insulation layer wherein the HDP insulation layer vertically sticks out above the gate trenches;

spacers attached to a top portion of the HDP insulation layer above the gate trenches and exposing a top surface of mesa areas of the semiconductor substrate between the gate trenches; and

each of the mesa areas between the gate trenches having a deep contact trench vertically aligned with the spacers and extending vertically below a top surface of the conductive materially partially filling the trench gate wherein the recessed contact trenches are filled with a source/body contact material.

2. The semiconductor power device of claim 1 wherein:

the spacers attached to the top portion of the HDP insulation layer above the gate trenches are configured to define mesa-center areas disposed substantially in a middle portion of the mesa areas for etching the deep contact trenches below the mesa-center areas.

3. The semiconductor power device of claim 2 wherein:

the deep contact trenches opened vertically in the semiconductor substrate below the mesa-center areas are filled a metal contact.

4. The semiconductor power device of claim 3 further comprising:

a contact implant region disposed in the semiconductor substrate below a bottom surface of each of the deep contact trenches.

5. The semiconductor power device of claim 3 further comprising:

a source region disposed in the semiconductor substrate surrounding and directly contacting each of the deep contact trenches filled with the source/body contact material.

6. The semiconductor power device of claim 5 further comprising:

a body region in the semiconductor substrate surrounding each of the deep contact trenches between the gate trenches and encompassing the source regions.

7. The semiconductor power device of claim 1 wherein:

the spacers are low temperature oxide (LTO) layer attached to the portion of the HDP insulation layer above the gate trenches.

8. The semiconductor power device of claim 6 wherein:

the body regions extend over regions of the semiconductor substrate between the gate trenches with the deep contact trench penetrating through the source regions contacting the contact implant regions disposed below the bottom surface of the contact trenches disposed in the body regions.

9. The semiconductor power device of claim 8 further comprising:

a source metal layer disposed on top of the HDP layer and the contact trenches in contact with the conductive material filling the contact trenches for electrically connected to the source regions and body regions.

10. The semiconductor power device of claim 8 further comprising:

a body clamping layer (BCL) of the same conductivity type as the body region extending vertically below a bottom surface of the gate trenches in a peripheral area of the active cell area.

11. The semiconductor power device of claim 3 wherein:

the contact trenches have a width substantially between 0.1 to 0.15 micrometers.

12. The semiconductor power device of claim 1 wherein:

the gate trenches have a width approximately 0.25 micrometers and a distance between adjacent gate trenches having a pitch approximately 0.5 micrometers.

13. The semiconductor power device of claim 1 further comprising:

a source metal layer covering over the active cell area and a gate metal layer covering over a termination area wherein the source metal and the gate metal are separated by a gap substantially aligned with one of the spacers adjacent one of the gate trenches functioning as a gate pickup trench disposed on an edge of the active cell area.