FINFET DEVICE AND FABRICATION METHOD THEREOF

• US 20180323300A1
• Filed: 05/04/2018
• Published: 11/08/2018
• Est. Priority Date: 05/05/2017
• Status: Active Grant

• Current Assignee: Semiconductor Manufacturing International Corporation
• Original Assignee: Semiconductor Manufacturing International Corporation
• Inventors: WANG, Nan, PAN, Zi Cheng, HONG, Zhong Shan
• Granted Patent: US 10,453,962 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/2253 by ion implantation
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/4232 with insulated gate
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/6681 using dummy structures having essentially the same shape as the semiconductor body, e.g. to provide stability
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7853 the body having a non-rectangular crossection

Abstract

A FinFET device and fabrication method thereof is provided. The method includes: providing a semiconductor substrate and fins. Each fin includes a first sidewall region and a second sidewall region. An interlayer dielectric layer is formed on the semiconductor substrate and on the fins, with openings. Then a target work function layer is formed on sidewalls and on a bottom of each opening. The target work function layer includes a first target region covering the first sidewall region, a second target region covering the second sidewall region, and a third portion on the top surface of each fin. The second target region and the third portion of the target work function layer is doped with modification ions; and has a second effective work function value greater than a first effective work function value of the first target region of the target work function layer.

Claims

1. A fabrication method for a FinFET, comprising:

providing a semiconductor substrate and fins on the semiconductor substrate, wherein each fin includes a first sidewall region and a second sidewall region above the first sidewall region;

forming an interlayer dielectric layer on the semiconductor substrate and on the fins, with openings in the interlayer dielectric layer to expose a portion of sidewalls and a portion of a top surface of each fin; and

forming a target work function layer on sidewalls and on a bottom of each opening, the target work function layer including a first target region covering the first sidewall region, a second target region covering the second sidewall region, and a third portion on the top surface of each fin, wherein;

the second target region and the third portion of the target work function layer is doped with modification ions; and

the first target region of the target work function layer has a first effective work function value, while the second target region and the third portion of the target work function layer has a second effective work function value greater than the first effective work function value.

2. The fabrication method according to claim 1, wherein each fin has a bottom width greater than a top width.

3. The fabrication method according to claim 2, wherein a ratio of a size of the first sidewall region over a size of the second sidewall region of a same sidewall of each fin in a direction parallel to the sidewalls of the fins and perpendicular to an extending direction of the fins is about 2:

5 to about 3;

5.

4. The fabrication method according to claim 1, wherein, when the FinFET device is P-type,

the first target region of the target work function layer is made of a material including TiN, TiC, and/or MoN, and

the second target region of the target work function layer is made of a material including TiN, TiC and/or MoN, and the second target region is doped with the modification ions.

5. The fabrication method according to claim 1, wherein, when the FinFET device is N-type,

the first target region of the target work function layer is made of a material including TiAl and/or TaAl, and

the second target region of the target work function layer is made of a material including TiAl and/or TaAl, and the second target region is doped with the modification ions.

6. The fabrication method according to claim 1, wherein the target work function layer is formed by:

forming an initial work function layer with a first effective work function value on the sidewalls and the bottom of each opening, wherein the initial work function layer includes a first initial region covering the first sidewall region and a second initial region covering the second sidewall region of each fin; and

implanting the modification ions into the second initial region of the initial work function layer and into a third portion of the initial work function layer on the top surface of each fin using an ion implantation process, to form the target work function layer;

wherein;

the first initial region of the initial work function layer forms the first target region of the target work function layer, and the second initial region of the initial work function layer forms the second target region of the target work function layer.

7. The fabrication method according to claim 6, wherein:

the initial work function layer is made of a material including TiN, TiC, and/or MoN, and

the modification ions include N ions, F ions, C ions, As ions, or a combination thereof.

8. The fabrication method according to claim 7, wherein the ion implantation process uses:

the modification ions of N ions;

an implantation energy of about 2.5 keV to about 4.5 keV;

an implantation dose of about 1E13 atom/cm² to about 1E15 atom/cm²;

a first implantation angle of about 10 degrees to about 40 degrees, and

a second implantation angle of about 0 degree to about 15 degrees,

wherein the first implantation angle is an angle between an implantation direction and a normal direction of a surface of the semiconductor substrate, and the second implantation angle is an angle between the implantation direction and an extending direction of the fins.

9. The fabrication method according to claim 7, wherein the ion implantation process uses:

the modification ions of F ions;

the implantation energy of about 3 keV to about 5 keV;

the implantation dose of about 1E13 atom/cm² to about 1E15 atom/cm²;

the first implantation angle of about 10 degrees to about 40 degrees, and

the second implantation angle of about 0 degree to about 15 degrees.

10. The fabrication method according to claim 7, wherein the ion implantation process uses:

the modification ions of carbon ions;

the implantation energy of about 2 keV to about 4 keV;

the implantation dose of about 1E13 atom/cm² to about 1E15 atom/cm²;

the first implantation angle of about 10 degrees to about 40 degrees, and

the second implantation angle of about 0 degree to about 15 degrees.

11. The fabrication method according to claim 7, wherein the ion implantation process uses:

the modification ions of As ions;

the implantation energy of about 8 keV to about 11 keV;

the implantation dose of about 1E13 atom/cm² to about 1E15 atom/cm²;

the first implantation angle of about 10 degrees to about 40 degrees, and

the second implantation angle of about 0 degree to about 15 degrees.

12. The fabrication method according to claim 6, wherein:

the initial work function layer is made of a material including TiAl and/or TaAl; and

the modification ions are Al ions or Ga ions.

13. The fabrication method according to claim 12, wherein the ion implantation process uses:

the modification ions of Al ions;

the implantation energy of about 6 keV to about 8 keV;

the implantation dose of about 1E13 atom/cm² to about 1E15 atom/cm²;

the first implantation angle of about 10 degrees to about 40 degrees, and

the second implantation angle of about 0 degree to about 15 degrees.

14. The fabrication method according to claim 12, wherein the ion implantation process uses:

the modification ions of Ga ions;

the implantation energy of about 7 keV to about 10 keV;

the implantation dose of about 1E13 atom/cm² to about 1E15 atom/cm²;

the first implantation angle of about 10 degrees to about 40 degrees, and

the second implantation angle of about 0 degree to about 15 degrees.

15. A FinFET device, comprising:

a semiconductor substrate;

fins on the semiconductor substrate, wherein each fin has a first sidewall region and a second sidewall region above the first sidewall region;

an interlayer dielectric layer on the semiconductor substrate and on the fins, containing openings to expose a portion of the sidewalls and a portion of the top surface of each fin; and

a target work function layer on sidewalls and a bottom of each opening.

16. The FinFET according to claim 15, wherein:

the target work function layer includes a first target region covering the first sidewall region, a second target region covering the second sidewall region, and a third portion on the top surface of each fin;

the second target region and the third portion of the target work function layer on the top surface of each fin is doped with modification ions; and

the first target region of the target work function layer has a first effective work function value, while the second target region and the third portion of the target work function has a second effective work function value greater than the first effective work function value.

17. The FinFET according to claim 15, wherein each fin has a bottom width greater than a top width.

18. The FinFET according to claim 15, wherein a ratio of a size of the first sidewall region over a size of the second sidewall region of a same sidewall of each fin in a direction parallel to the sidewalls of the fins and perpendicular to an extending direction of the fins is about 2:

5 to about 3;

5.

19. The FinFET according to claim 15, wherein, when the FinFET device is P-type,

the first target region of the target work function layer is made of a material including TiN, TiC, and/or MoN, and

the second target region of the target work function layer is made of a material including TiN, TiC and/or MoN, and the second target region is doped with the modification ions.

20. The FinFET according to claim 15, wherein, when the FinFET device is N-type,

the first target region of the target work function layer is made of a material including TiAl and/or TaAl, and

the second target region of the target work function layer is made of a material including TiAl and/or TaAl, and the second target region is doped with the modification ions.