FLAT DISPLAY PANEL AND METHOD OF MANUFACTURING THE SAME

• US 20180329248A1
• Filed: 05/15/2018
• Published: 11/15/2018
• Est. Priority Date: 05/15/2017
• Status: Active Grant

• Current Assignee: LG Display Co., Ltd.
• Original Assignee: LG Display Co., Ltd.
• Inventors: CHO, Suk-Ho
• Granted Patent: US 10,712,594 B2
• Time in Patent Office: Days
• CPC Class Codes: G02F 1/13318 Circuits comprising a photodetector
• CPC Class Codes: G02F 1/133345 Insulating layers G02F1/1335, G02F1/1337, G02F1/135, G02F1/136 take precedence
• CPC Class Codes: G02F 1/133357 Planarisation layers
• CPC Class Codes: G02F 1/136227 Through-hole connection of the pixel electrode to the active element through an insulation layer
• CPC Class Codes: G02F 1/136286 Wiring, e.g. gate line, drain line
• CPC Class Codes: G02F 1/136295 Materials; Compositions; Manufacture processes
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence
• CPC Class Codes: H01L 21/0274 Photolithographic processes
• CPC Class Codes: H01L 21/32133 by chemical means only
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1248 with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
• CPC Class Codes: H01L 27/1262 with a particular formation, treatment or coating of the substrate
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H10K 59/13 comprising photosensors that control luminance
• CPC Class Codes: H10K 59/60 OLEDs integrated with inorganic light-sensitive elements, e.g. with inorganic solar cells or inorganic photodiodes

Abstract

Disclosed are a flat display panel that is capable of preventing a different appearance between a camera index light source (CIL) and an ambient light sensor hole and a method of manufacturing the same. The flat display panel is configured such that, on a first substrate, partitioned into a pixel region of a display area and a CIL hole part and an ambient light sensor hole part of a non-display area, a gate insulating layer, a first passivation film, a planarization film, and a second passivation film are not present at the CIL hole part or at the ambient light sensor hole part or such that only the planarization film is present at the CIL hole part and the ambient light sensor hole part.

Claims

1. A flat display panel, comprising:

a first substrate, partitioned into a pixel region in a display area and a camera index light source hole region and an ambient light sensor hole region in a non-display area;

a thin film transistor on a surface of the first substrate in the pixel region, the thin film transistor having a gate electrode, a gate insulating layer, an active layer, and source/drain electrodes;

a first passivation film and a planarization film sequentially stacked on the surface of the first substrate, the first passivation film and the planarization film at least partially overlying the thin film transistor;

a second passivation film overlying the surface of the first substrate; and

a pixel electrode on the second passivation film in the pixel region, the pixel electrode electrically connected to the drain electrode via a contact hole which extends through the second passivation film, the planarization film, and the first passivation film above the drain electrode,

wherein at least one of the camera index light source hole region and the ambient light sensor hole region includes a cavity that extends through the gate insulating layer, the first passivation film, the planarization film, and the second passivation film.

2. The flat display panel according to claim 1, further comprising a common electrode and a common line formed in the pixel region between the planarization film and the second passivation film.

3. The flat display panel according to claim 1 wherein each of the camera index light source hole region and the ambient light sensor hole region includes a respective cavity that extends through the gate insulating layer, the first passivation film, the planarization film, and the second passivation film.

4. A flat display panel, comprising:

a first substrate, partitioned into a pixel region in a display area and a camera index light source hole region and an ambient light sensor hole region in a non-display area;

a thin film transistor on a surface of the first substrate in the pixel region, the thin film transistor having a gate electrode, a gate insulating layer, an active layer, and source/drain electrodes;

a first passivation film and a planarization film sequentially stacked on the surface of the first substrate, the first passivation film and the planarization film at least partially overlying the thin film transistor;

a second passivation film overlying the surface of the first substrate; and

a pixel electrode on the second passivation film in the pixel region, the pixel electrode electrically connected to the drain electrode via a contact hole which extends through the second passivation film, the planarization film, and the first passivation film above the drain electrode,

wherein at least one of the camera index light source hole region and the ambient light sensor hole region includes a cavity that extends through the gate insulating layer and the first passivation film, the planarization film being formed on the first substrate in the cavity of the at least one of the camera index light source hole region and the ambient light sensor hole region.

5. The flat display panel according to claim 4, further comprising a common electrode and a common line formed in the pixel region between the planarization film and the second passivation film.

6. A method of manufacturing a flat display panel, comprising:

preparing a first substrate, partitioned into a pixel region in a display area and a camera index light source hole region and an ambient light sensor hole region in a non-display area;

forming a gate electrode on the first substrate in the pixel region;

forming a gate insulating layer on an entire surface of the first substrate in the pixel region, the camera index light source hole region, and the ambient light sensor hole region;

forming an active layer and source/drain electrodes on the gate insulating layer in the pixel region;

sequentially forming a first passivation film and a planarization film over the entire surface of the first substrate in the pixel region, the camera index light source hole region, and the ambient light sensor hole region;

selectively removing the planarization film above the drain electrode, the camera index light source hole region, and the ambient light sensor hole region;

forming a second passivation film over the entire surface of the first substrate in the pixel region, the camera index light source hole region, and the ambient light sensor hole region;

removing the first passivation film and the second passivation film above the drain electrode, the camera index light source hole region, and the ambient light sensor hole region; and

forming a pixel electrode on the second passivation film in the pixel region, the pixel electrode being electrically connected to the drain electrode.

7. The method according to claim 6, further comprising forming a common electrode and a common line in the pixel region between the planarization film and the second passivation film.

8. A method of manufacturing a flat display panel, comprising:

preparing a first substrate, partitioned into a pixel region in a display area and a camera index light source hole region and an ambient light sensor hole region in a non-display area;

forming a gate electrode on the first substrate in the pixel region;

forming a gate insulating layer on an entire surface of the first substrate in the pixel region, the camera index light source hole region, and the ambient light sensor hole region;

forming an active layer and source/drain electrodes on the gate insulating layer in the pixel region;

forming a first passivation film over the entire surface of the first substrate in the pixel region, the camera index light source hole region, and the ambient light sensor hole region;

selectively removing the gate insulating layer and the first passivation film above the camera index light source hole region and the ambient light sensor hole region;

forming a planarization film over the entire surface of the first substrate;

selectively removing the planarization film above the drain electrode;

forming a second passivation film over the entire surface of the first substrate in the pixel region, the camera index light source hole region, and the ambient light sensor hole region;

removing the first passivation film and the second passivation film above the drain electrode;

removing the second passivation film above the camera index light source hole region and the ambient light sensor hole region; and

forming a pixel electrode on the second passivation film in the pixel region, the pixel electrode being electrically connected to the drain electrode.

9. The method according to claim 8, further comprising forming a common electrode and a common line in the pixel region between the planarization film and the second passivation film.