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Gate Driver for Depletion-Mode Transistors

  • US 20180331682A1
  • Filed: 07/24/2018
  • Published: 11/15/2018
  • Est. Priority Date: 06/22/2016
  • Status: Abandoned Application
First Claim
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1. A deadtime circuit comprising:

  • an upper delay block coupled to a PWM signal and a tap of the upper delay block coupled to an upper gate driver;

    a lower leading edge (LE) delay block having a plurality of LE delay taps and coupled to an inverted PWM signal line;

    a lower LE multiplexer coupled to the plurality of LE delay taps of the lower LE delay block and configured to select one of the plurality of the LE delay taps responsive to a lower LE address for output to a lower LE delay signal line;

    a lower trailing edge (TE) delay block having a plurality of delay taps and coupled to the inverted PWM signal line;

    a lower TE multiplexer coupled to the plurality of delay taps of the lower TE delay block and configured to select one of the plurality of the TE delay taps responsive to a lower TE address for output to a lower TE delay signal line;

    a latch, inputs of the latch coupled to the lower LE delay signal line and the lower TE delay signal line, an output coupled to a lower gate driver; and

    a deadtime state machine configured to;

    output a lower LE address to the lower LE multiplexer for selecting a LE delay tap,output a lower TE address to the lower TE multiplexer for selecting a LE delay tap,receive an upper gate drive sense signal from output of the upper gate driver,receive a lower gate drive sense signal from output of the lower gate driver,calculate a LE deadtime based on the upper and lower gate drive sense signals, andincrease the LE address if the LE deadtime is greater than a target deadtime, or store the LE address in non-volatile memory (NVM) if the LE deadtime is not greater than the target LE deadtime.

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