Gate Driver for Depletion-Mode Transistors

• US 20180331682A1
• Filed: 07/24/2018
• Published: 11/15/2018
• Est. Priority Date: 06/22/2016
• Status: Abandoned Application

• Current Assignee: Sarda Technologies, Inc.
• Original Assignee: Sarda Technologies, Inc.
• Inventors: Duduman, Bogdan M., Fogg, John K.
• Application Number:
  US16/043,188
• Publication Number:
  US 20180331682A1
• Time in Patent Office: Days
• CPC Class Codes: H02M 1/32 Means for protecting converters other than automatic disconnection
• CPC Class Codes: H02M 1/327 against abnormal temperatures
• CPC Class Codes: H02M 1/38 Means for preventing simultaneous conduction of switches
• CPC Class Codes: H02M 3/07 using capacitors charged and discharged alternately by semiconductor devices with control electrode , e.g. charge pumps
• CPC Class Codes: H02M 3/1588 comprising at least one synchronous rectifier element H02M3/1582, H02M3/1584 take precedence
• CPC Class Codes: H03K 17/063 in field-effect transistor switches
• CPC Class Codes: H03K 17/223 in field-effect transistor switches
• CPC Class Codes: H03K 2017/066 Maximizing the OFF-resistance instead of minimizing the ON-resistance
• CPC Class Codes: H03K 5/19 Monitoring patterns of pulse trains indicating amplitude G01R19/00; indicating frequency G01R23/00; measuring characteristics of individual pulses G01R29/02
• CPC Class Codes: H03K 7/08 Duration or width modulation ; Duty cycle modulation
• CPC Class Codes: Y02B 70/10 Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

The present disclosure presents a circuit, method, and system for dynamically determining optimal deadtime values in a DC-DC converter power stage while operating the circuit under controlled conditions during a test/trim routine. The determined optimal deadtime values are stored in non-volatile memory. The optimal deadtime values are used as fixed settings during normal PWM operation. On start-up, the optimal, fixed deadtime values are loaded into the deadtime circuits of the driver and used during normal PWM operation of the DC-DC converter power stage circuit.

Claims

1. A deadtime circuit comprising:

an upper delay block coupled to a PWM signal and a tap of the upper delay block coupled to an upper gate driver;

a lower leading edge (LE) delay block having a plurality of LE delay taps and coupled to an inverted PWM signal line;

a lower LE multiplexer coupled to the plurality of LE delay taps of the lower LE delay block and configured to select one of the plurality of the LE delay taps responsive to a lower LE address for output to a lower LE delay signal line;

a lower trailing edge (TE) delay block having a plurality of delay taps and coupled to the inverted PWM signal line;

a lower TE multiplexer coupled to the plurality of delay taps of the lower TE delay block and configured to select one of the plurality of the TE delay taps responsive to a lower TE address for output to a lower TE delay signal line;

a latch, inputs of the latch coupled to the lower LE delay signal line and the lower TE delay signal line, an output coupled to a lower gate driver; and

a deadtime state machine configured to;

output a lower LE address to the lower LE multiplexer for selecting a LE delay tap,

output a lower TE address to the lower TE multiplexer for selecting a LE delay tap,

receive an upper gate drive sense signal from output of the upper gate driver,

receive a lower gate drive sense signal from output of the lower gate driver,

calculate a LE deadtime based on the upper and lower gate drive sense signals, and

increase the LE address if the LE deadtime is greater than a target deadtime, or store the LE address in non-volatile memory (NVM) if the LE deadtime is not greater than the target LE deadtime.

2. The deadtime circuit of claim 1, wherein the deadtime state machine is further configured to:

place the deadtime circuit in test mode for receiving the TE address and LE address;

place the deadtime circuit in a step mode to receive the upper and lower gate drive sense signals; and

place the deadtime circuit in test mode to store the TE address in NVM.

3. The deadtime circuit of claim 1, wherein the deadtime state machine is further configured to:

output a lower TE address to the lower TE multiplexer for selecting a TE delay tap;

output a lower TE address to the lower TE multiplexer for selecting a TE delay tap;

receive an upper gate drive sense signal from output of the upper gate driver;

receive a lower gate drive sense signal from output of the lower gate driver;

calculate a TE deadtime based on the upper and lower gate drive sense signals; and

increase the TE address if the TE deadtime is greater than a target deadtime, or store the TE address in non-volatile memory (NVM) if the TE deadtime is not greater than the target TE deadtime.

4. The deadtime circuit of claim 1, wherein the upper delay block is adjustable responsive to an upper address.

5. The deadtime circuit of claim 1, further comprising an upper multiplexer coupled to a plurality of delay taps of the upper delay block and configured to select the tap of the upper delay block coupled to an upper gate driver responsive to an upper address.

6. A deadtime adjustment system comprising:

an upper gate driver coupled to a delayed Pulse Width Modulated (PWM) signal and an upper gate of a DC-DC converter power stage circuit;

a first adjustable delay circuit coupled to the PWM signal and configured to output a first delayed PWM signal responsive to a first delay address;

a second adjustable delay circuit coupled to the PWM signal and configured to output a second delayed PWM signal responsive to a second delay address;

a latch configured to receive the first and second delayed PWM signals and output a lower PWM signal via a lower gate driver to a lower gate of the DC-DC converter power stage circuit; and

a deadtime state machine including circuits and logic programmed to;

operate in a step mode comprising;

applying the first address from a working register to the first adjustable delay circuit,

receiving an upper gate drive sense signal derived from the upper gate driver and a lower gate drive sense signal derived from the lower gate driver,

measuring a first deadtime using the upper and lower gate drive sense signals, and

if the first deadtime is greater than a target first deadtime, increment or decrement the first address in the working register to decrease the first deadtime, and repeat the step mode using the decreased first deadtime, or

if the first deadtime is not greater than the target first edge deadtime, store the first address in non-volatile memory (NVM), and exit the step mode; and

operate in a test mode comprising;

receiving values for working registers including an initial first address, an initial second address, a target first edge deadtime, and a target second edge deadtime, and

outputting a fixed first address from NVM to the first addressable delay circuit.

7. The deadtime adjustment system of claim 6, wherein the step mode further comprises:

outputting the second address from a working register to the second adjustable delay circuit;

receiving an upper gate drive sense signal derived from the upper gate driver and a lower gate drive sense signal derived from the lower gate driver;

measuring a second deadtime using the upper and lower gate drive sense signals; and

if the second deadtime is greater than a target second deadtime, increment or decrement the second address in the working register to decrease the second deadtime, and repeat the step mode;

or

if the second deadtime is not greater than the target second edge deadtime, store the second address in non-volatile memory (NVM), and exit the step mode.

8. The deadtime adjustment system of claim 7, wherein the PWM signal is coupled to the upper gate driver via an upper delay circuit.

9. The deadtime adjustment system of claim 8, wherein upper delay circuit is adjustable.

10. The deadtime adjustment system of claim 8, wherein upper delay circuit is adjustable responsive to an upper delay address received from the deadtime state machine.

11. The deadtime adjustment system of claim 6, wherein NVM is a circuit in the deadtime state machine.

12. A method for adjusting deadtime in a DC-DC converter power stage circuit, the method comprising:

placing the DC-DC converter power stage circuit in test mode;

loading a delay address to a delay circuit that produces a deadtime output from the deadtime circuit greater than a target deadtime;

placing the DC-DC converter power stage circuit in step mode;

stepping through delay addresses to progressively reduce the deadtime output of the deadtime circuit until the deadtime output of the deadtime circuit is less than the target deadtime; and

placing the DC-DC converter power stage circuit in test mode;

storing a deadtime value corresponding to the currently loaded delay address in non-volatile memory of the DC-DC converter power stage circuit.

13. The method of claim 12, further comprising:

exporting the currently loaded delay address to an automated test machine; and

receiving from the automated test machine a deadtime value based on the delay address and an instruction to store the delay value in the non-volatile memory.

14. The method of claim 12, wherein stepping through delay addresses comprises at each step:

placing the DC-DC converter power stage circuit in PWM mode;

operating the DC-DC converter power stage circuit in PWM mode for a predetermined number of PWM cycles;

determining deadtime output of the deadtime circuit for the step;

comparing the determined deadtime output of the deadtime circuit to the target deadtime; and

placing the DC-DC converter power stage circuit in test mode.

15. The method of claim 12, further comprising:

loading the stored deadtime value to the delay address of the deadtime circuit; and

initializing a signal to initiate a normal operation mode of the DC-DC converter power stage circuit.

16. The method of claim 12, further comprising:

initializing a signal to initiate a normal operation mode of the DC-DC converter power stage circuit;

loading the stored deadtime value to the delay address of the deadtime circuit;

initializing a signal to initiate a startup mode of the DC-DC converter power stage circuit; and

upon completion of the startup mode initializing a signal to initiate a normal operation mode of the DC-DC converter power stage circuit.

17. A system for adjusting deadtime of a DC-DC converter power stage circuit, the method comprising:

a delay circuit coupled to a PWM signal and a lower gate of the DC-DC converter power stage circuit;

means for loading an initial delay address to the delay circuit that corresponds to a maximum deadtime output from the delay circuit while operating in test mode;

means for progressively decreasing deadtime output from the delay circuit by stepping through delay addresses loaded to the delay circuit while operating in a step mode;

means for determining for each progressive loaded deadtime address if the deadtime output of the delay circuit is less than a target deadtime;

non-volatile memory (NVM) for storing a fixed deadtime value corresponding to the delay address loaded for the deadtime output determined to be less than the target deadtime; and

means for loading the fixed deadtime value from NVM to the delay circuit for operation in PWM mode.

18. The system of claim 17, wherein the means for loading a delay address includes a working register.

18-1. The system of claim 18, wherein the working register is a counter.

20. The system of claim 17, wherein the fixed deadtime value stored in the NVM is the delay address that is first loaded for the deadtime output determined to be less than the target deadtime.