SHIFT REGISTER CIRCUIT, WAVEFORM GENERATING METHOD FOR SAME, AND DISPLAY PANEL USING THE SAME

• US 20180336859A1
• Filed: 05/31/2017
• Published: 11/22/2018
• Est. Priority Date: 05/12/2017
• Status: Active Grant

• Current Assignee: Chongqing HKC Optoelectronics Technology Co., Ltd. (Shenzhen Huike Investment Holding Co., Ltd.), HKC Corporation Limited (Shenzhen Huike Investment Holding Co., Ltd.)
• Original Assignee: Chongqing HKC Optoelectronics Technology Co., Ltd. (Shenzhen Huike Investment Holding Co., Ltd.), HKC Corporation Limited (Shenzhen Huike Investment Holding Co., Ltd.)
• Inventors: CHEN, Yu-Jen
• Granted Patent: US 10,453,412 B2
• Time in Patent Office: Days
• CPC Class Codes: G09G 2310/0286 Details of a shift registers arranged for use in a driving circuit
• CPC Class Codes: G09G 2320/0214 with crosstalk due to leakage current of pixel switch in active matrix panels
• CPC Class Codes: G09G 2330/04 Display protection
• CPC Class Codes: G09G 3/3677 suitable for active matrices only
• CPC Class Codes: G09G 3/3696 Generation of voltages supplied to electrode drivers
• CPC Class Codes: G11C 19/28 using semiconductor elements G11C19/14, G11C19/36 take precedence

Abstract

This application provides a shift register circuit, a waveform generating method for same, and a display panel using same. The shift register circuit includes a plurality of stages of shift registers, including: a first switch, including a control end of the first switch electrically coupled to a first node, a first end of the first switch electrically coupled to a frequency signal, and a second end of the first switch is electrically coupled to an output pulse signal; a second switch, including a control end of the second switch electrically coupled to an input pulse signal, a first end of the second switch electrically coupled to the input pulse signal, and a second end of the second switch electrically coupled to the first node; a third switch, including a control end of the third switch electrically coupled to a second node, a first end of the third switch is electrically coupled to the output pulse signal, and a second end of the third switch is electrically coupled to a preset low potential; and a fourth switch, including a control end of the fourth switch is electrically coupled to the second node, a first end of the fourth switch is electrically coupled to the first node, and a second end of the fourth switch is electrically coupled to the preset low potential, a length of an internal channel between the first end of the fourth switch and the second end of the fourth switch is increased, or an internal channel between the first end of the fourth switch and the second end of the fourth switch is designed as dual channels.

Claims

1. A shift register circuit, comprising a plurality of stages of shift registers, wherein each shift register comprises:

a first switch, including a control end of the first switch electrically coupled to a first node, a first end of the first switch electrically coupled to a frequency signal, and a second end of the first switch electrically coupled to an output pulse signal;

a second switch, including a control end of the second switch electrically coupled to an input pulse signal, a first end of the second switch electrically coupled to the input pulse signal, and a second end of the second switch electrically coupled to the first node;

a third switch, including a control end of the third switch electrically coupled to a second node, a first end of the third switch electrically coupled to the output pulse signal, and a second end of the third switch electrically coupled to a preset low potential; and

a fourth switch, including a control end of the fourth switch electrically coupled to the second node, a first end of the fourth switch electrically coupled to the first node, and a second end of the fourth switch electrically coupled to the preset low potential, wherein a length of an internal channel between the first end of the fourth switch and the second end of the fourth switch is increased, or an internal channel between the first end of the fourth switch and the second end of the fourth switch is designed as dual channels.

2. The shift register circuit according to claim 1, wherein further comprising a compensation circuit, comprising a fifth switch, the fifth switch including a control end of the fifth switch electrically coupled to the output pulse signal, a first end of the fifth switch electrically coupled to the output pulse signal, and a second end of the fifth switch electrically coupled to the preset low potential.

3. The shift register circuit according to claim 1, further comprising a pull-down sub-circuit, electrically coupled to the first node, the output pulse signal, and the preset low potential of the shift register.

4. The shift register circuit according to claim 3, further comprising a pull-down sub-circuit controller electrically coupled to the preset low potential and the pull-down sub-circuit of the shift register.

5. The shift register circuit according to claim 2, wherein the compensation circuit is configured to reduce a potential difference between the control end of the fourth switch and the first end of the fourth switch.

6. A waveform generating method for a shift register circuit, applied to a plurality of stages of shift registers, wherein the shift register comprises a first switch, a second switch, a third switch, a fourth switch, a compensation circuit, a pull-down sub-circuit and a pull-down sub-circuit controller, wherein the first switch is configured to generate an output signal of the shift register and provide the output signal to a next-stage shift register, and the waveform generating method comprising:

conducting the first switch, and pulling up a potential of an output end of the shift register by using a frequency signal;

reducing a potential difference between a control end of the fourth switch and a first end of the fourth switch by adding the compensation circuit; and

pulling down the potential of the output end of the shift register by means of an input pulse signal by using the second switch and the pull-down sub-circuit.

7. The waveform generating method for a shift register circuit according to claim 6, wherein the step of reducing a potential difference between a control end of the fourth switch and a first end of the fourth switch by adding the compensation circuit comprises:

adding a fifth switch to the shift register, wherein a control end of the fifth switch is electrically coupled to an output pulse signal, a first end of the fifth switch is electrically coupled to the output pulse signal, and a second end of the fifth switch is electrically coupled to a preset low potential.

8. The waveform generating method for a shift register circuit according to claim 6, further comprising a pull-down sub-circuit, electrically coupled to a first node, the output pulse signal and the preset low potential of the shift register.

9. The waveform generating method for a shift register circuit according to claim 6, further comprising a pull-down sub-circuit controller, electrically coupled to the preset low potential and the pull-down sub-circuit of the shift register.

10. The waveform generating method for a shift register circuit according to claim 6, wherein the compensation circuit is configured to reduce the potential difference between the control end of the fourth switch and the first end of the fourth switch.

11. A display panel, comprising:

a first substrate;

a plurality of pixels, formed on the first substrate;

a shift register circuit, comprising a plurality of stages of shift registers, wherein each shift register comprises;

a first switch, including a control end of the first switch electrically coupled to a first node, a first end of the first switch electrically coupled to a frequency signal, and a second end of the first switch electrically coupled to an output pulse signal;

a second switch, including a control end of the second switch is electrically coupled to an input pulse signal, a first end of the second switch electrically coupled to the input pulse signal, and a second end of the second switch electrically coupled to the first node;

a third switch, including a control end of the third switch electrically coupled to a second node, a first end of the third switch electrically coupled to the output pulse signal, and a second end of the third switch electrically coupled to a preset low potential; and

a fourth switch, including a control end of the fourth switch electrically coupled to the second node, a first end of the fourth switch electrically coupled to the first node, and a second end of the fourth switch electrically coupled to the preset low potential, wherein

a length of an internal channel between the first end of the fourth switch and the second end of the fourth switch is increased, or an internal channel between the first end of the fourth switch and the second end of the fourth switch is designed as dual channels; and

the shift register circuit is disposed on the first substrate.

12. The display panel according to claim 11, further comprising a compensation circuit, comprising a fifth switch, the fifth switch including a control end of the fifth switch electrically coupled to the output pulse signal, a first end of the fifth switch electrically coupled to the output pulse signal, and a second end of the fifth switch electrically coupled to the preset low potential.

13. The display panel according to claim 11, further comprising a pull-down sub-circuit, electrically coupled to the first node, the output pulse signal, and the preset low potential of the shift register.

14. The display panel according to claim 13, further comprising a pull-down sub-circuit controller, electrically coupled to the preset low potential and the pull-down sub-circuit of the shift register.

15. The display panel according to claim 12, wherein the compensation circuit is configured to reduce a potential difference between the control end of the fourth switch and the first end of the fourth switch.