MITIGATION OF TIME DEPENDENT DIELECTRIC BREAKDOWN

• US 20180337053A1
• Filed: 05/18/2017
• Published: 11/22/2018
• Est. Priority Date: 05/18/2017
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: HUANG, Yi-Jyun, YOUNG, Bao-Ru, HSIEH, Tung-Heng
• Granted Patent: US 10,658,486 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/28105 the final conductor next to the insulator having a lateral composition or doping variation, or being formed laterally by more than one deposition step
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/4983 with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66553 using inside spacers, permanent or not
• CPC Class Codes: H01L 29/66871 Processes wherein the final gate is made after the formation of the source and drain regions in the active layer, e.g. dummy-gate processes
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence

Abstract

The present disclosure describes an exemplary replacement gate process that forms spacer layers in a gate stack to mitigate time dependent dielectric breakdown (TDDB) failures. For example, the method can include a partially fabricated gate structure with a first recess. A spacer layer is deposited into the first recess and etched with an anisotropic etchback (EB) process to form a second recess that has a smaller aperture than the first recess. A metal fill layer is deposited into the second recess.

Claims

1. A method, comprising:

forming a gate structure with a first recess over a substrate, wherein the first recess has a bottom surface;

depositing a spacer layer into the first recess, wherein the spacer layer comprises a dielectric;

etching the spacer layer with an anisotropic etchback process to expose the bottom surface of the first recess and form, based on the spacer layer covering inside surfaces of the first recess, a second recess smaller than the first recess; and

depositing a metal into the second recess.

2. The method of claim 1, wherein the forming the gate structure comprises:

forming a dummy gate stack over the substrate;

forming a gate spacer along a sidewall of the dummy gate stack;

removing the dummy gate stack to form an opening exposing the substrate, the gate spacer defining a sidewall of the opening, and

conformally depositing an other dielectric in the opening; and

conformally depositing a multiple gate metal stack over the other dielectric to form the first recess.

3. The method of claim 2, wherein the other dielectric comprises a high-k dielectric.

4. The method of claim 2, wherein the multiple gate metal stack comprises a capping layer, one or more metallic layers, and a work function metal stack.

5. The method of claim 1, wherein the depositing the spacer layer comprises depositing the spacer layer using a chemical vapor deposition (CVD), an atomic layer deposition (ALD), or a plasma-enhanced CVD (PECVD) process.

6. The method of claim 1, wherein the dielectric comprises silicon nitride (Si₃N₄), silicon oxynitride (SiON), carbon-doped silicon nitride (SiCN), or silicon oxycarbide (SiO_xC_y).

7. The method of claim 1, wherein the metal comprises a titanium nitride (TiN) layer and a tungsten (W) metal stack.

8. A structure, comprising:

a substrate;

two opposing spacers on the substrate;

a first dielectric disposed over the substrate between the two opposing spacers;

a second dielectric conformally deposited between the two opposing spacers and over the first dielectric;

a multiple gate metal stack conformally deposited over the second dielectric to form a first recess with two opposing side surfaces;

a spacer layer disposed over the two opposing side surfaces of the first recess to form a second recess smaller than the first recess, wherein the spacer layer comprises a third dielectric; and

a metal deposited into the second recess.

9. The structure of claim 8, wherein the spacer layer has a thickness range up to 2.5 nm.

10. The structure of claim 8, wherein the third dielectric comprises silicon nitride (Si₃N₄), silicon oxynitride (SiON), carbon-doped silicon nitride (SiCN), or silicon oxycarbide (SiO_xC_y).

11. The structure of claim 8, wherein the metal comprises a titanium nitride (TiN) layer and a tungsten (W) metal stack.

12. The structure of claim 8, wherein the first recess comprises an aperture between 10 nm and 15 nm, and the second recess comprises an aperture up to 5 nm.

13. The structure of claim 8, wherein two opposing spacers have a height between 20 nm and 25 nm.

14. The structure of claim 8, wherein the first dielectric comprises an interfacial oxide.

15. The structure of claim 8, wherein the second dielectric comprises a high-k dielectric.

16. The structure of claim 8, wherein the multiple gate metal stack comprises a capping layer, one or more metallic layers, and a work function metal stack.

17. A method, comprising:

providing a substrate;

forming two opposing spacers on the substrate;

forming a first dielectric over the substrate between the two opposing spacers;

depositing conformally a second dielectric between the two opposing spacers and over the first dielectric;

depositing conformally a multiple gate metal stack over the second dielectric to form a first recess with two opposing side surfaces;

depositing a spacer layer over the two opposing side surfaces of the first recess to form a second recess smaller than the first recess, wherein the spacer layer comprises a third dielectric; and

depositing a metal into the second recess.

18. The method of claim 17, wherein the forming the spacer layer comprises forming the spacer laying using a chemical vapor deposition (CVD), an atomic layer deposition (ALD), or a plasma-enhanced CVD (PECVD) process.

19. The method of claim 17, wherein the third dielectric comprises silicon nitride (Si₃N₄), silicon oxynitride (SiON), carbon-doped silicon nitride (SiCN), or silicon oxycarbide (SiO_xC_y).

20. The method of claim 17, wherein forming the spacer layer comprises forming the spacer layer using an anisotropic etchback process with a carbon fluoride (CF_x) based chemistry and an etch rate up to 5 Å

/sec.