Fin Field Effect Transistor (FinFET) Device Structure and Method for Forming the Same

• US 20180337095A1
• Filed: 07/31/2018
• Published: 11/22/2018
• Est. Priority Date: 07/02/2015
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chen, Chang-Yin, Chang, Chai-Wei, Young, Bo-Feng, Chen, Yi-Jen
• Granted Patent: US 10,854,519 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/32137 of silicon-containing layers
• CPC Class Codes: H01L 21/762 Dielectric regions , e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823437 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/823462 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/6681 using dummy structures having essentially the same shape as the semiconductor body, e.g. to provide stability
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A FinFET device structure and method for forming the same are provided. The FinFET device structure includes a fin structure formed over a substrate and a gate structure traversing over the fin structure. The gate structure includes a gate electrode layer which includes an upper portion above the fin structure and a lower portion below the fin structure, the virtual surface is formed between the upper portion and the lower portion, and the lower portion has a tapered width which is gradually tapered from the virtual interface to a bottom surface of the lower portion.

Claims

1. A method for forming a fin field effect transistor (FinFET) device structure, comprising:

forming a fin structure over a substrate;

forming an isolation structure over the substrate, wherein a portion of the fin structure is embedded in the isolation structure; and

forming a gate structure over the fin structure and the isolation structure, wherein the gate structure comprises a gate electrode layer which comprises an upper portion above the fin structure and a lower portion below an upper surface of the fin structure, and the lower portion has a tapered width which is gradually tapered from a virtual interface to a bottom surface of the lower portion, the virtual interface is formed between the upper portion and the lower portion.

2. The method of claim 1, wherein forming the gate structure over the fin structure and the isolation structure comprises:

forming a gate material over the fin structure and the isolation structure;

forming a hard mask layer over the gate material;

patterning the hard mask layer; and

etching the gate material by using the hard mask layer as a mask to form the gate structure.

3. The method of claim 2, wherein etching the gate material comprises using an etching process at a pressure in a range from about 10 torr to about 100 torr.

4. The method of claim 2, wherein the etching is performed using an etching gas, wherein a ratio of an amount of the etching gas in an edge region of the substrate to that of the etching gas in an overall region is in a range from about 50 vol. % to about 90 vol. %.

5. The method of claim 1, wherein forming the gate structure comprises:

forming a dummy gate structure;

forming an inter-layer dielectric (ILD) structure over the substrate and adjacent to the dummy gate structure;

removing the dummy gate structure to form a trench in the ILD structure; and

forming a gate dielectric layer and a gate electrode layer in the trench to form the gate structure.

6. The method of claim 5, further comprising epitaxially growing source/drain regions after forming the dummy gate structure.

7. A method for forming a fin field effect transistor (FinFET) device structure, comprising:

forming a fin structure over a substrate;

forming an isolation structure over the substrate, wherein the fin structure protrudes above an upper surface of the isolation structure;

forming a first layer over the fin structure and the isolation structure; and

etching the first layer to form a first gate such that a sidewall of the first gate is narrower adjacent the isolation structure than an upper surface of the first gate.

8. The method of claim 7, wherein the etching is performed using a plasma etching process.

9. The method of claim 8 wherein the plasma etching process uses HBR as an etching gas.

10. The method of claim 9, wherein a flow rate of the etching gas is in a range from about 700 sccm to about 1000 sccm.

11. The method of claim 10, wherein the plasma etching process is performed at a power in a range from about 350 Watt to about 1500 Watt.

12. The method of claim 11, wherein the plasma etching process is performed at a pressure in a range from about 10 torr to about 100 torr.

13. The method of claim 8, wherein a ratio of an amount of an etching gas in an edge region of the substrate to that of the etching gas in an overall region is in a range from about 50 vol. % to about 90 vol. %.

14. A method for forming a fin field effect transistor (FinFET) device structure, comprising:

forming a fin structure over a substrate;

forming an isolation structure over the substrate, wherein the fin structure protrudes above an upper surface of the isolation structure;

forming a dummy gate layer over the fin structure and the isolation structure;

patterning the dummy gate layer to form a dummy gate, wherein the dummy gate has a virtual interface between an upper portion and a lower portion, the lower portion having a tapered width that is gradually tapered from the virtual interface to a bottom surface of the lower portion;

forming a first spacer along a first sidewall of the dummy gate and a second spacer along a second sidewall of the dummy gate;

forming a dielectric layer adjacent the first spacer and the second spacer;

removing the dummy gate; and

forming a gate electrode between the first spacer and the second spacer.

15. The method of claim 14, wherein the upper portion has a top surface with a first width, and the lower portion has a bottom surface with a second width, and the first width is greater than the second width.

16. The method of claim 15, wherein the virtual interface has a third width, and the third width is greater than the second width.

17. The method of claim 14, wherein the virtual interface is substantially level with a top surface of the fin structure.

18. The method of claim 14, wherein the upper portion of the gate electrode has substantially vertical sidewalls.

19. The method of claim 14, wherein the upper portion of the gate electrode has a first height from the virtual interface to an upper surface of the gate electrode, and the lower portion of the gate electrode has a second height from the virtual interface to a bottom surface of the gate electrode, and the first height is greater than the second height.

20. The method of claim 14, wherein the gate electrode overlaps an end of the fin structure.