SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

• US 20180337127A1
• Filed: 07/31/2018
• Published: 11/22/2018
• Est. Priority Date: 12/17/2015
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chang, Che-Cheng, Lin, Chih-Han, Tseng, Horng-Huei
• Granted Patent: US 10,643,947 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/76831 in via holes or trenches, e.g. non-conductive sidewall liners
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 21/823425 manufacturing common source or drain regions between a plurality of conductor-insulator-semiconductor structures
• CPC Class Codes: H01L 21/823475 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 23/485 consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts H01L23/4821, H01L23/4822, H01L23/4824, H01L23/4825 take precedence; materials H01L23/532, bond pads H01L24/02, bump connectors H01L24/10
• CPC Class Codes: H01L 23/535 including internal interconnections, e.g. cross-under constructions internal lead connections H01L23/481
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain

Abstract

A semiconductor structure includes a substrate, a first gate structure, a first spacer, a source drain structure, a first dielectric layer, a conductor, and a protection layer. The first gate structure is present on the substrate. The first spacer is present on a sidewall of the first gate structure. The source drain structure is present adjacent to the first spacer. The first dielectric layer is present on the first gate structure and has an opening therein, in which the source drain structure is exposed through the opening. The conductor is electrically connected to the source drain structure, in which the conductor has an upper portion in the opening of the first dielectric layer and a lower portion between the upper portion and the source drain structure. The protection layer is present between the lower portion and the first spacer and between the upper portion and the source drain structure.

Claims

1. A method for manufacturing a semiconductor structure, the method comprising:

forming a first dielectric layer over a gate structure and over a source drain structure adjacent to the gate structure;

forming a recess in the first dielectric layer over the source drain structure;

forming a protection layer over the first dielectric layer, the protection layer lining sidewalls and a bottom of the recess;

deepening the recess to expose the source drain structure;

forming a bottom conductor in the recess and connected to the source drain structure;

forming a second dielectric layer over the gate structure and over the bottom conductor;

forming an opening in the second dielectric layer to expose the bottom conductor; and

forming an upper conductor in the opening and connected to the bottom conductor.

2. The method of claim 1, wherein forming the recess comprises removing a first portion of the first dielectric layer disposed directly over the source drain structure, wherein after removing the first portion of the first dielectric layer, a second portion of the first dielectric layer remains under the recess.

3. The method of claim 2, wherein deepening the recess comprises performing an isotropic etch process.

4. The method of claim 2, wherein deepening the recess removes portions of the protection layer over the first dielectric layer, portions of the protection layer lining the bottom of the recess, and portions of the second portion of the first dielectric layer, wherein after deepening the recess, a remaining portion of the protection layer lines upper sidewalls of the recess, and a remaining portion of the second portion of the first dielectric layer lines lower sidewalls of the recess.

5. The method of claim 4, wherein forming the bottom conductor comprises:

filling an electrically conductive material in the recess after deepening the recess; and

after the filling, removing the first dielectric layer, an upper portion of the remaining portion of the protection layer, and an upper portion of the electrically conductive material, wherein a remaining portion of the electrically conductive material forms the bottom conductor.

6. The method of claim 5, wherein after the bottom conductor is formed, the remaining portion of the second portion of the first dielectric layer extends along a sidewall of the gate structure.

7. The method of claim 1, wherein the protection layer is formed of silicon nitride, silicon oxynitride, or combinations thereof.

8. The method of claim 1, wherein the protection layer and the first dielectric layer are formed of different materials.

9. The method of claim 8, wherein the first dielectric layer and the second dielectric layer are formed of a same material.

10. The method of claim 1, wherein forming the recess comprises performing a photolithography and etching process.

11. The method of claim 1, wherein the recess is formed to have a sloped upper sidewall and a straight lower sidewall.

12. The method of claim 11, wherein forming the protection layer comprises forming the protection layer along the sloped upper sidewall of the recess and along the straight lower sidewall of the recess, wherein the protection layer has a sloped upper portion with slopped upper sidewall, and has a straight lower portion with a straight lower sidewall, wherein an upper surface of the sloped upper portion of the protection layer is level with an upper surface of a mask layer disposed on the gate structure.

13. A method for manufacturing a semiconductor structure, the method comprising:

depositing a first dielectric material over a semiconductor device, the semiconductor device comprising;

a gate structure;

a mask layer over the gate structure;

a spacer along a sidewall of the gate structure and along a sidewall of the mask layer; and

a source drain structure adjacent to the gate structure, wherein the first dielectric material is deposited over the mask layer and the source drain structure;

forming a recess in the first dielectric material directly over the source drain structure, wherein after the recess is formed, a first portion of the first dielectric material underlies the recess and covers the source drain structure;

forming a protection layer lining sidewalls and a bottom of the recess;

performing an anisotropic etch process to deepen the recess, wherein the source drain structure is exposed after the anisotropic etch process; and

filling the recess with a first conductive material to form a bottom conductor.

14. The method of claim 13, wherein the anisotropic etch process removes portions of the first portion of the first dielectric material, wherein the anisotropic etch process leaves a remaining portion of the first portion of the first dielectric material along a sidewall of the spacer.

15. The method of claim 13, further comprising:

after forming the bottom conductor, forming a second dielectric material over the mask layer and the bottom conductor;

forming an opening in the second dielectric material to expose the bottom conductor; and

filling the opening with a second conductive material to form an upper conductor.

16. The method of claim 13, wherein the recess has a sloped upper sidewall and a straight lower sidewall, wherein the protection layer has a sloped upper portion along the sloped upper sidewall of the recess, and has a straight lower portion along the straight lower sidewall of the recess, wherein after the bottom conductor is formed, an upper surface of the sloped upper portion of the protection layer is level with an upper surface of the mask layer.

17. A method for manufacturing a semiconductor structure, the method comprising forming a first dielectric layer over a gate structure and over a source drain structure adjacent to the gate structure;

forming a recess in the first dielectric layer over the source drain structure, a bottom of the recess being between the source drain structure and an upper surface of the first dielectric layer;

forming a protection layer along sidewalls and a bottom of the recess;

deepening the recess by an anisotropic etch process to expose the source drain structure, wherein the anisotropic etch process removes the protection layer from the bottom of the recess, wherein after the anisotropic etch process, a remaining portion of the first dielectric layer extends along a sidewall of the gate structure;

filling a first metal in the recess to form a bottom conductor that is electrically coupled to the source drain structure;

forming a second dielectric layer over the gate structure and over the bottom conductor;

forming an opening in the second dielectric layer to expose the bottom conductor; and

filling a second metal in the opening to form an upper conductor that is electrically coupled to the bottom conductor.

18. The method of claim 17, wherein there is a gate spacer disposed along the sidewall of the gate structure, wherein forming the recess comprises performing an etching process, wherein the etching process removes a portion of the gate spacer such that after the etching process, an upper portion of the gate spacer has a sloped sidewall and a lower portion of the gate spacer has a straight sidewall.

19. The method of claim 17, wherein after the anisotropic etch process, the protection layer has an upper portion in physical contact with the upper portion of the gate spacer, and has an lower portion in physical contact with the lower portion of the gate spacer, wherein the upper portion of the protection layer has a sloped sidewall, and the lower portion of the protection layer has a straight sidewall.

20. The method of claim 17, wherein the first dielectric layer and the second dielectric layer are formed of a same material, wherein the first dielectric layer and the protection layer are formed of different materials.