CHARGE PUMP FOR DISTRIBUTED VOLTAGE PASSGATE WITH HIGH VOLTAGE PROTECTION

• US 20180337669A1
• Filed: 05/17/2017
• Published: 11/22/2018
• Est. Priority Date: 05/17/2017
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Cheruiyot, Kennedy K., Muench, Paul D., Sperling, Michael A., Whalen, Michael R.
• Granted Patent: US 10,644,497 B2
• Time in Patent Office: Days
• CPC Class Codes: H02H 7/16 for capacitors for synchronous capacitors H02H7/06
• CPC Class Codes: H02M 1/32 Means for protecting converters other than automatic disconnection
• CPC Class Codes: H02M 3/07 using capacitors charged and discharged alternately by semiconductor devices with control electrode , e.g. charge pumps
• CPC Class Codes: H03K 17/08142 in field-effect transistor switches
• CPC Class Codes: H03K 19/0016 by using a control or a clock signal, e.g. in order to apply power supply
• CPC Class Codes: H03K 2217/0054 Gating switches, e.g. pass gates
• CPC Class Codes: H03K 2217/0081 Power supply means, e.g. to the switch driver

Abstract

Embodiments include a technique for using a charge pump for a distributed voltage passgate with high voltage protection. The technique includes receiving a reference signal, and preventing the reference signal from passing through a passgate to a circuit, wherein the passgate is an NFET passgate. The technique also includes charging the passgate using a charge pump circuit above the reference signal, and regulating the charge pump circuit using a clock signal. The technique also includes controlling the passgate based at least in part on the charge pump circuit.

Claims

1. A method for using a charge pump for a distributed voltage passgate with high voltage protection, the method comprising:

receiving a reference signal;

preventing the reference signal from passing through a passgate to a circuit, wherein the passgate is an n-channel field-effect transistor (NFET) passgate;

charging the passgate using a charge pump circuit above the reference signal;

regulating the charge pump circuit using a clock signal; and

controlling the passgate based at least in part on the charge pump circuit.

2. The method of claim 1, further comprising protecting the charge pump circuit using a high voltage protection transistor.

3. The method of claim 1, further comprising powering on the charge pump circuit to activate the passgate.

4. The method of claim 1, further comprising powering off the charge pump circuit to drain the charge pump circuit down to zero volts and turning off the passgate.

5. The method of claim 1, wherein the clock signal used by the charge pump circuit comprises a first signal and a second clock signal.

6. The method of claim 5, wherein the first clock signal is opposite the second clock signal.

7. The method of claim 5, wherein the first clock signal and the second clock signal are non-overlapping signals.

8. The method of claim 1, further comprising holding a voltage of the passgate when the charge pump circuit is on.

9. A system using a charge pump for a distributed voltage passgate with high voltage protection, the system comprising:

a reference circuit for generating a reference signal to be used by a core of a multiprocessor chip;

a charge pump circuit operable to generate a voltage to drive the passgate, wherein the voltage is greater than a voltage of the reference signal; and

a passgate operable to control transmission of a reference signal to the core of the multiprocessor chip, wherein the passgate is an n-channel field-effect transistor (NFET) passgate.

10. The system of claim 9, the system comprises one or more high voltage protection transistors for protecting the charge pump circuit.

11. The system of claim 9, wherein the charge pump circuit uses a capacitor to maintain a voltage of the charge pump circuit for the passgate.

12. The system of claim 9, wherein the reference signal is an analog signal.

13. The system of claim 9, wherein the charge pump circuit includes a power supply voltage equal to 1000 mV.

14. The system of claim 9, wherein a passgate threshold voltage is 300 mV.

15. The system of claim 9, wherein a first clock signal and a second clock signal of the charge pump circuit are non-overlapping clock signals.

16. The system of claim 9, wherein the passgate resides on each core of a multi-core processor.

17. The system of claim 15, wherein a gate voltage of the passgate and a source voltage of the passgate toggles between an NFET threshold voltage and a NFET threshold voltage plus a power supply voltage based on the clock.