SEMICONDUCTOR DEVICE, LIQUID CRYSTAL DISPLAY DEVICE, AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD

• US 20180341138A1
• Filed: 08/02/2018
• Published: 11/29/2018
• Est. Priority Date: 09/10/2014
• Status: Active Grant

• Current Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Original Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Inventors: KATOH, Sumio, UEDA, Naoki
• Granted Patent: US 10,451,946 B2
• Time in Patent Office: Days
• CPC Class Codes: G02F 1/133345 Insulating layers G02F1/1335, G02F1/1337, G02F1/135, G02F1/136 take precedence
• CPC Class Codes: G02F 1/134309 characterised by their geometrical arrangement
• CPC Class Codes: G02F 1/134372 for fringe field switching [FFS] where the common electrode is not patterned
• CPC Class Codes: G02F 1/13439 characterised by their electrical, optical, physical properties; materials therefor; method of making
• CPC Class Codes: G02F 1/136209 Light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally associated with the switching element
• CPC Class Codes: G02F 1/136218 Shield electrodes
• CPC Class Codes: G02F 1/136227 Through-hole connection of the pixel electrode to the active element through an insulation layer
• CPC Class Codes: G02F 1/136286 Wiring, e.g. gate line, drain line
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence
• CPC Class Codes: G02F 2201/121 common or background
• CPC Class Codes: G02F 2201/123 pixel
• CPC Class Codes: G02F 2202/02 organic material
• CPC Class Codes: G02F 2202/10 semiconductor
• CPC Class Codes: H01L 21/28 Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268 etching for patterning the electrodes H01L21/311, H01L21/3213; multistep manufacturing processes for data storage electrodes H01L29/4011
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/1248 with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
• CPC Class Codes: H01L 29/41733 for thin film transistors with insulated gate
• CPC Class Codes: H01L 29/786 Thin film transistors, i.e. transistors with a channel being at least partly a thin film transistors having only the source or the drain region on an insulator layer H01L29/0653; thin film FinFETs H01L29/785
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

A semiconductor device includes: a first metal layer including a gate electrode; a first insulating layer provided on the first metal layer; an oxide semiconductor layer provided on the first insulating layer; a second insulating layer provided on the oxide semiconductor layer; a second metal layer provided on the oxide semiconductor layer and the second insulating layer, the second metal layer including a source electrode; a third insulating layer provided on the second metal layer; and a first transparent electrode layer provided on the third insulating layer. The oxide semiconductor layer includes a first portion lying above the gate electrode and a second portion extending from the first portion so as to lie across an edge of the gate electrode on the drain electrode side. The third insulating layer does not include an organic insulating layer. The second insulating layer and the third insulating layer have a first contact hole which overlaps the second portion of the oxide semiconductor layer when viewed in a normal direction of the substrate. The first transparent electrode layer includes a transparent electrically-conductive layer which is in contact with the second portion of the oxide semiconductor layer in the first contact hole.

Claims

1. A semiconductor device including a substrate and a thin film transistor supported by the substrate, the thin film transistor including a gate electrode, a source electrode and a drain electrode, the semiconductor device comprising:

an oxide semiconductor layer including an active layer of the thin film transistor;

a first insulating layer provided on the oxide semiconductor layer;

a first metal layer provided on the first insulating layer, the first metal layer including the gate electrode of the thin film transistor;

a second insulating layer provided on the first metal layer;

a second metal layer provided on the second insulating layer, the second metal layer including at least the source electrode;

a third insulating layer provided on the second metal layer; and

a first transparent electrode layer provided on the third insulating layer,

wherein the oxide semiconductor layer includes a first portion lying above the gate electrode and a second portion extending from the first portion so as to lie across an edge of the gate electrode on the drain electrode side,

the third insulating layer does not include an organic insulating layer,

the first insulating layer, the second insulating layer and the third insulating layer have a first contact hole which overlaps the second portion of the oxide semiconductor layer when viewed in a normal direction of the substrate, and

the first transparent electrode layer includes a transparent electrically-conductive layer which is in contact with the second portion of the oxide semiconductor layer in the first contact hole.

2. The semiconductor device of claim 1, wherein

the second metal layer further includes the drain electrode, and

the first contact hole also overlaps an end portion of the drain electrode on the second portion side when viewed in the normal direction of the substrate.

3. The semiconductor device of claim 1, wherein the second metal layer does not include the drain electrode.

4. The semiconductor device of claim 1, wherein

the semiconductor device includes a plurality of pixels,

each of the plurality of pixels includes the thin film transistor and the transparent electrically-conductive layer, and

the transparent electrically-conductive layer functions as a pixel electrode.

5. The semiconductor device of claim 4, further comprising:

a fourth insulating layer covering the first transparent electrode layer; and

a second transparent electrode layer provided on the fourth insulating layer,

wherein the second transparent electrode layer includes a transparent electrode which is electrically separated from the pixel electrode, the transparent electrode being capable of functioning as a common electrode.

6. The semiconductor device of claim 5, wherein

the second metal layer further includes an upper wire layer,

the third insulating layer and the fourth insulating layer have a second contact hole which overlaps the upper wire layer when viewed in the normal direction of the substrate,

the second transparent electrode layer further includes a transparent connecting layer which is electrically coupled with the common electrode, and

the transparent connecting layer is in contact with the upper wire layer in the second contact hole.

7. The semiconductor device of claim 5, wherein

the second metal layer includes an upper wire layer,

the third insulating layer and the fourth insulating layer have a second contact hole which overlaps the upper wire layer when viewed in the normal direction of the substrate,

the first transparent electrode layer further includes a first transparent connecting layer which is electrically separated from the pixel electrode,

the second transparent electrode layer further includes a second transparent connecting layer which is electrically coupled with the common electrode,

the first transparent connecting layer is in contact with the upper wire layer in the second contact hole, and

the second transparent connecting layer is in contact with the first transparent connecting layer in the second contact hole.

8. The semiconductor device of claim 4, further comprising:

a fourth insulating layer provided between the third insulating layer and the first transparent electrode layer, and

a second transparent electrode layer provided between the third insulating layer and the fourth insulating layer,

wherein the first contact hole is provided also in the fourth insulating layer, and

the second transparent electrode layer includes a transparent electrode which is electrically separated from the pixel electrode, the transparent electrode being capable of functioning as a common electrode.

9. The semiconductor device of claim 1, further comprising:

a fourth insulating layer provided on the first transparent electrode layer; and

a second transparent electrode layer provided on the fourth insulating layer,

wherein the first contact hole is also provided in the fourth insulating layer,

the first transparent electrode layer further includes a first electrode which is electrically separated from the transparent electrically-conductive layer, and

the second transparent electrode layer includes a second electrode which is in contact with the transparent electrically-conductive layer in the first contact hole.

10. The semiconductor device of claim 9, wherein

the semiconductor device includes a plurality of pixels,

each of the plurality of pixels includes the thin film transistor, the first electrode and the second electrode,

the first electrode functions as a common electrode, and

the second electrode functions as a pixel electrode.

11. The semiconductor device of claim 1, wherein the oxide semiconductor layer includes an In—

Ga—

Zn—

O based semiconductor.

12. The semiconductor device of claim 11, wherein the In—

Ga—

Zn—

O based semiconductor includes a crystalline portion.

13. A liquid crystal display device, comprising:

an active matrix substrate;

a counter substrate which opposes the active matrix substrate; and

a liquid crystal layer provided between the active matrix substrate and the counter substrate,

wherein the active matrix substrate is the semiconductor device as set forth in claim 1.

14. A manufacturing method of a semiconductor device, the semiconductor device including a substrate and a thin film transistor supported by the substrate, the thin film transistor including a gate electrode, a source electrode and a drain electrode, the method comprising the steps of:

(a) forming an oxide semiconductor layer on the substrate, the oxide semiconductor layer including an active layer of the thin film transistor;

(b) forming a first insulating layer on the oxide semi-conductor layer;

(c) forming a first metal layer on the first insulating layer, the first metal layer including the gate electrode of the thin film transistor;

(d) forming a second insulating layer on the first metal layer;

(e) forming a second metal layer on the second insulating layer, the second metal layer including at least the source electrode;

(f) forming a third insulating layer on the second metal layer;

(g) forming a contact hole in the first insulating layer, the second insulating layer and the third insulating layer; and

(h) after step (g), forming a transparent electrode layer on the third insulating layer,

wherein the oxide semiconductor layer formed in step (a) includes a first portion lying above the gate electrode and a second portion extending from the first portion so as to lie across an edge of the gate electrode on the drain electrode side,

the third insulating layer formed in step (f) does not include an organic insulating layer,

the contact hole formed in step (g) overlaps the second portion of the oxide semiconductor layer when viewed in a normal direction of the substrate, and

the transparent electrode layer formed in step (h) includes a transparent electrically-conductive layer which is in contact with the second portion of the oxide semiconductor layer in the contact hole.

15. The manufacturing method of claim 14, wherein

the second metal layer formed in step (e) further includes the drain electrode, and

the contact hole formed in step (g) also overlaps an end portion of the drain electrode on the second portion side when viewed in the normal direction of the substrate.

16. The manufacturing method of claim 14, wherein the second metal layer formed in step (e) does not include the drain electrode.

17. The manufacturing method of claim 14, wherein the oxide semiconductor layer includes an In—

Ga—

Zn—

O based semi-conductor.

18. The manufacturing method of claim 17, wherein the In—

Ga—

Zn—

O based semiconductor includes a crystalline portion.