DUAL CLUSTERS OF FULLY CONNECTED INTEGRATED CIRCUIT MULTIPROCESSORS WITH SHARED HIGH-LEVEL CACHE

• US 20180341587A1
• Filed: 11/01/2017
• Published: 11/29/2018
• Est. Priority Date: 05/26/2017
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Blake, Michael A., Bronson, Timothy C., Mak, Pak-kin, Papazova, Vesselina K., Sonnelitter, III, Robert J.
• Granted Patent: US 10,628,314 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 12/0811 with multilevel cache hierarchies
• CPC Class Codes: G06F 12/0813 with a network or matrix configuration
• CPC Class Codes: G06F 12/0826 Limited pointers directories; State-only directories without pointers
• CPC Class Codes: G06F 12/084 with a shared cache
• CPC Class Codes: G06F 12/0862 with prefetch
• CPC Class Codes: G06F 2212/1024 Latency reduction
• CPC Class Codes: G06F 2212/314 In storage network, e.g. network attached cache
• CPC Class Codes: G06F 2212/602 Details relating to cache prefetching

Abstract

Embodiments of the present invention are directed to managing a shared high-level cache for dual clusters of fully connected integrated circuit multiprocessors. An example of a computer-implemented method includes: providing a drawer comprising a plurality of clusters, each of the plurality of clusters comprising a plurality of processors; providing a shared cache integrated circuit to manage a shared cache memory among the plurality of clusters; receiving, by the shared cache integrated circuit, an operation of one of a plurality of operation types from one of the plurality of processors; and processing, by the shared cache integrated circuit, the operation based at least in part on the operation type of the operation according to a set of rules for processing the operation type.

Claims

1. A computer-implemented method comprising:

providing a drawer comprising a plurality of clusters, each of the plurality of clusters comprising a plurality of processors, each of the plurality of processors comprising a plurality of processing cores having a private Level 1 cache and a private Level 2 cache, the processing cores within each of the plurality of clusters sharing a shared Level 3 cache;

providing a single shared cache integrated circuit to manage a shared Level 4 cache memory among the plurality of clusters;

receiving, by the single shared cache integrated circuit, an operation of one of a plurality of operation types from one of the plurality of processors; and

processing, by the single shared cache integrated circuit, the operation based at least in part on the operation type of the operation according to a set of rules for processing the operation type.

2. The computer-implemented method of claim 1, wherein the operation type is a fetch type operation.

3. The computer-implemented method of claim 1, wherein the operation is an input/output store type operation.

4. The computer-implemented method of claim 1, wherein the single shared cache integrated circuit comprises a directory to store a plurality of directory state bits.

5. The computer-implemented method of claim 4, wherein the directory state bits are used to process the operation according to the set of rules for processing the operation type.

6. The computer-implemented method of claim 1, wherein each of the plurality of processors is connected to the single shared cache integrated circuit.

7. The computer-implemented method of claim 1, wherein each of the plurality of processors is connected to each of the other of the plurality of processors within its cluster.