Word Line Pulse Width Control Circuit in Static Random Access Memory
First Claim
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1. A control circuit for minimizing a static noise margin of a static random access memory device comprising:
- a first transistor comprising a gate and a source/drain terminal;
an inverter comprising an input node coupled to the gate of the first transistor and an output node; and
a second transistor comprising a gate and a source/drain terminal, the gate of the second transistor being coupled to the output node of the inverter and the source/drain terminal of the second transistor being coupled to the source/drain terminal of the first transistor.
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Abstract
Devices and methods are provided for word line pulse width control for a static random access memory (SRAM) devices. An inverter within a pre-decoder circuit receives a first input of a clocked address. The inverter determines an output based on the clocked address. An electrical load of a decoder driver circuit of the SRAM device is modified based on the output. Current to a transistor coupled at a common node is provided. The transistor is configured to electrically couple a plurality of transistors of the decoder driver circuit within the SRAM device.
55 Citations
20 Claims
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1. A control circuit for minimizing a static noise margin of a static random access memory device comprising:
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a first transistor comprising a gate and a source/drain terminal; an inverter comprising an input node coupled to the gate of the first transistor and an output node; and a second transistor comprising a gate and a source/drain terminal, the gate of the second transistor being coupled to the output node of the inverter and the source/drain terminal of the second transistor being coupled to the source/drain terminal of the first transistor. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A static random access memory (SRAM) device comprising:
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at least two decoder driver circuits electrically coupled together via a common decoder line; a transistor electrically coupled to the common decoder line; and an inverter electrically coupled to the transistor. - View Dependent Claims (8, 9, 10, 11, 12, 13)
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14. A method in a static random access memory (SRAM) device comprising:
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receiving, by an inverter, a first input comprising a clocked address; determining, by the inverter, an output based on the clocked address; modifying an electrical load of a decoder driver circuit of the SRAM device based on the output; and providing current to a transistor coupled at a common node configured to electrically couple a plurality of transistors within the decoder driver circuit. - View Dependent Claims (15, 16, 17, 18, 19, 20)
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Specification