METHOD FOR ASSESSING THE USABILITY OF AN EXPOSED AND DEVELOPED SEMICONDUCTOR WAFER

• US 20180342429A1
• Filed: 06/25/2018
• Published: 11/29/2018
• Est. Priority Date: 08/17/2015
• Status: Active Grant

• Current Assignee: Qoniac GmbH (KLA Corporation)
• Original Assignee: Qoniac GmbH (KLA Corporation)
• Inventors: Habets, Boris, Roessiger, Martin, Buhl, Stefan
• Granted Patent: US 10,699,971 B2
• Time in Patent Office: Days
• CPC Class Codes: G03F 7/70483 Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
• CPC Class Codes: G03F 7/705 Modelling or simulating from physical phenomena up to complete wafer processes or whole workflow in wafer productions
• CPC Class Codes: G03F 7/70558 Dose control, i.e. achievement of a desired dose
• CPC Class Codes: G03F 7/70625 Dimensions, e.g. line width, critical dimension [CD], profile, sidewall angle or edge roughness
• CPC Class Codes: G03F 7/70633 Overlay, i.e. relative alignment between patterns printed by separate exposures in different layers, or in the same layer in multiple exposures or stitching
• CPC Class Codes: G03F 7/70641 Focus
• CPC Class Codes: H01L 21/0274 Photolithographic processes
• CPC Class Codes: H01L 22/12 for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions electrical measurement of diffusions H01L22/14
• CPC Class Codes: H01L 22/20 Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps

Abstract

An apparatus and a method for analysis of processing of a semiconductor wafer is disclosed which comprises gathering a plurality of items of processing data, applying at least one process model to the at least some of the plurality of items of processing data to derive at least one set of process results, comparing at least some of the derived sets of process results or at least some of the plurality of items of processing data with a process window, and outputting a set of comparison results based on the comparison of the derived sets of process results or the plurality of items of processing data with the process window.

Claims

1. A method for the processing of a further layer on a semiconductor wafer comprising:

depositing at least one photoresist layer on a surface of a lower layer,

exposing to radiation the at least one photoresist layer;

removing at least part of the exposed photoresist layer to leave a pattern;

measuring a plurality of items of processing data, some of the plurality of items of processing data being measured on the semiconductor wafer, the processing data further including lens errors and/or errors made in the use of the projection system;

applying at least one process model to the at least some of the plurality of items of processing data to derive a set of process results, the process results comprising an error in focus, an error in radiation dosage, and a change in a contact area between different ones of the structural elements of the semiconductor wafer;

comparing at least one of the derived set of process results or at least one of the plurality of items of processing data with a process window, the process window encompassing the at least one of the derived set of process results or the at least one of the plurality of items of processing data; and

at least one of accepting or reworking the further layer, based on the comparison.

2. The method of claim 1, wherein the items of processing data are further selected from the set of processing data consisting of overlay errors, critical dimensions, levelling measurements, deposition thickness, etching times, etching depths, line edge roughness (LER), line width roughness (LWR), side wall angle, other geometry data of patterns, wafer shape and/or deformation, temperature of hot plates, defect measurements, exposure dose, focus/exposure dose measurement, electrical measurements, as well as further derived data derived from one or more of the processing data.

3. The method of claim 1, further comprising adaptation of the process window based on the comparison result.

4. The method of claim 1, further comprising amending at least one process parameter based on the comparison result.

5. The method of claim 1, wherein the comparison result comprises at least one of a measurement instruction, re-working of the processed layer, or yield prediction.

6. The method of claim 1, wherein the comparison result delivers a probability value.

7. The method of claim 1, wherein the comparison result is compared with a threshold value.

8. The method of claim 1, wherein the at least one of accepting or reworking the further layer is determined by a threshold value for at least one or more of the derived set of process results or the plurality of items of processing data.

9. The method of claim 1, further comprising depositing a further photoresist layer and exposing the further photoresist layer.

10. The method of claim 9, comprising forming a spacer on a sidewall of at least one element of the pattern.

11. A method for the processing of a further layer on a semiconductor wafer comprising:

depositing at least one photoresist layer on a surface of a lower layer,

exposing to radiation the at least one photoresist layer;

removing at least part of the exposed photoresist layer to leave a pattern;

measuring a plurality of items of processing data, some of the plurality of items of processing data being measured on the semiconductor wafer;

applying at least one process model to the at least some of the plurality of items of processing data to derive a set of process results, at least some of the process results relating to a three-dimensional structure of the semiconductor wafer;

comparing at least one of the derived set of process results or at least one of the plurality of items of processing data with a process window, the process window encompassing the at least one of the derived set of process results or the at least one of the plurality of items of processing data; and

at least one of accepting or reworking the further layer, based on the comparison.

12. The method of claim 11, wherein the applying of at least one process model to the at least some of the plurality of items of processing data further comprises simulating electrical properties of the three-dimensional structure.

13. The method of claim 11, wherein the items of processing data are further selected from the set of processing data consisting of overlay errors, critical dimensions, levelling measurements, deposition thickness, etching times, etching depths, line edge roughness (LER), line width roughness (LWR), side wall angle, other geometry data of patterns, wafer shape and/or deformation, temperature of hot plates, defect measurements, exposure dose, focus/exposure dose measurement, electrical measurements, as well as further derived data derived from one or more of the processing data.

14. The method of claim 11, further comprising adaptation of the process window based on the comparison result.

15. The method of claim 11, further comprising amending at least one process parameter based on the comparison result.

16. The method of claim 11, wherein the comparison result comprises at least one of a measurement instruction, re-working of the processed layer, or yield prediction.

17. The method of claim 11, wherein the comparison result delivers a probability value.

18. The method of claim 11, wherein the comparison result is compared with a threshold value.

19. The method of claim 11, wherein the at least one of accepting or reworking the further layer is determined by a threshold value for at least one or more of the derived set of process results or the plurality of items of processing data.

20. The method of claim 11, further comprising depositing a further photoresist layer and exposing the further photoresist layer.

21. The method of claim 20, comprising forming a spacer on a sidewall of at least one element of the pattern.

22. The method of claim 11, further comprising

storing the derived set of process results and/or the comparison results in the storage memory, and

comparing the stored and derived set of process results and/or the stored comparison results with data stored in a yield management system, wherein the data include yield data and data from electrical verification measurements.